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 ## Project name
 
-The Libre-RISCV SoC, Formal Correctness Proofs
+The Libre RISC-V SoC, Formal Correctness Proofs
 
 ## Website / wiki 
 
@@ -19,7 +19,7 @@ if you need any HTML to make your point please include this as attachment.
 
 ## Abstract: Can you explain the whole project and its expected outcome(s).
 
-The Libre RISC-V SoC is being developed to provide a privacy-respecting
+The Libre RISCV SoC is being developed to provide a privacy-respecting
 modern processor, developed transparently and as libre to the bedrock
 as possible.  
 
@@ -44,15 +44,15 @@ EUR 50,000.
 
 # Explain what the requested budget will be used for? 
 
-Working with mathematically-minded Software Engineers, every module in the Libre RISCV SoC will have a "formal proof unit test written". This is an unusual design choice: most hardware designs will have monte carlo and corner case unit tests etc. written which, unfortunately, are both complex and often incomplete.
+Working with mathematically-minded Software Engineers, every module in the Libre RISC-V SoC will have a "formal proof unit test written". This is an unusual design choice: most hardware designs will have monte carlo and corner case unit tests etc. written which, unfortunately, are both complex (and a distraction) and often incomplete.
 
 Examples include the IEEE754 Floating Point Unit, where in the 1990s Intel managed to introduce an actual hardware division bug. We seek to formally *prove* that the output from the FP Divide unit outputs the correct answer, for all possible inputs.
 
-There are other areas which can benefit from correctness proofs, at the low level: pipelines, FIFOs, the basic building blocks. On this stable foundation the higher level capabilities will then also get their own proofs.
+There are other areas which can benefit from correctness proofs, at the low level: pipelines, FIFOs, the basic building blocks of a processor. nmigen, interestingly, already has a formal correctness proof for its FIFO library due to the complexity of testing FIFOs.  On this stable foundation the higher level capabilities will then also get their own proofs.
 
-Finally a high level formal proof will be run, which already exists in the form of RISCV Conformance Tests, as well as unofficial formal correctness tests from SymbioticEDA.
+Finally a high level formal proof will be run, which already exists in the form of "official" RISC-V Conformance Tests (if it does not depend on proprietary software), as well as the unofficial formal correctness test suite from SymbioticEDA.
 
-Throughout this process, bugs will be found, including in code already written. These will require fixing, where previously it was believed that the work was completed.
+Throughout this process, bugs will be found, including in code already written. These will require fixing, where previously, with non-mathematical unit tests, it was believed that the work was completed.
 
 # Does the project have other funding sources, both past and present?
 
@@ -62,13 +62,15 @@ of the RTL (the hardware source code).
 
 The formal correctness testing requires specialist expertise involving formal logic mathematical training, which is a different skillset from hardware design. Our initial proposal does not cover this scope.
 
+Also not covered in the initial funding is the bugfixing that will be required should the more rigorous formal proofs discover any issues.
+
 # Compare your own project with existing or historical efforts.
 
-There do exist high level formal RISCV Correctness proofs in various forms. One of these is the SymbioticEDA formal RISCV proof which can for example test the Register File, and test that the integer operation is correct and so on, working its way through all operations one by one.  This however is at a high level.
+There do exist high level formal RISC-V Correctness proofs in various forms. One of these is the SymbioticEDA formal RISC-V proof which can for example test the Register File, and test that the integer operation is correct and so on, working its way through all operations one by one.  This however is at a high level.
 
 The Kestrel 53000 Series of embedded controllers have some formal unit tests written in verilog, at the lowest level. We are following their development and porting to nmigen closely, and consulting with their part time developer.
 
-A massive comprehensive suite of formal correctness proofs for a processor of the scope and size of the Libre RISCV SoC is just not normally done. The only reason we are considering it is because of the dramatic simplification of unit tests that the approach brings, and the mathematically inviolate guarantees it brings for endusers and developers.
+A massive comprehensive suite of formal correctness proofs for a processor of the scope and size of the Libre RISC-V SoC is just not normally done. The only reason we are considering it is because of the dramatic simplification of unit tests that the approach brings, and the mathematically inviolate guarantees it brings for endusers and developers.
 
 ## What are significant technical challenges you expect to solve during the project, if any?