(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 9d5b98a109531a63af7e1d6ff3f2233181c8fc12..9419a6d9f9e161ffa8b51ff81b20a79426b3426f 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -401,7 +401,6 @@ Vectorised
 Branch-Conditional attempted to merge the functionality of `svstep`
 into `sv.bc`: it became CISC-like in its complexity and was quickly reverted.
 
-\newpage{}
 # Simple-V REMAP subsystem
 
 [REMAP](https://libre-soc.org/openpower/sv/remap)
@@ -412,12 +411,13 @@ convoluted to implement.  They are typically implemented
 as hard-coded fully loop-unrolled assembler which is often
 auto-generated by specialist dedicated tools, or written
 entirely by hand.
-
 All REMAP Schedules *including Indexed*
 are 100% Deterministic from their point of declaration,
 making it possible to forward-plan
 Issue, Memory access and Register Hazard Management
 in Multi-Issue Micro-architectures.
+If combined with Vertical-First then much more complex operations may exploit
+REMAP Schedules, such as Complex Number FFTs.
 
 * **DCT/FFT** REMAP brings more capability than TI's MSP-Series DSPs and
   Qualcom Hexagon DSPs, and is not restricted to Integer or FP.
@@ -436,6 +436,7 @@ in Multi-Issue Micro-architectures.
 * **Parallel Reduction** REMAP, performs an automatic map-reduce using
   *any suitable scalar operation*.
 
+\newpage{}
 # Scalar Operations
 
 The primary reason for mentioning the additional Scalar operations