#include <unistd.h>
#define VMW_MAX_DEFAULT_TEXTURE_SIZE (128 * 1024 * 1024)
-#define VMW_FENCE_TIMEOUT_SECONDS 60
+#define VMW_FENCE_TIMEOUT_SECONDS 3600UL
#define SVGA3D_FLAGS_64(upper32, lower32) (((uint64_t)upper32 << 32) | lower32)
#define SVGA3D_FLAGS_UPPER_32(svga3d_flags) (svga3d_flags >> 32)
uint32_t handle;
uint64_t map_handle;
void *data;
+ uint32_t map_count;
int drm_fd;
uint32_t size;
};
req->version = drm_vmw_gb_surface_v1;
req->multisample_pattern = multisamplePattern;
req->quality_level = qualityLevel;
+ req->buffer_byte_stride = 0;
req->must_be_zero = 0;
req->base.svga3d_flags = SVGA3D_FLAGS_LOWER_32(flags);
req->svga3d_flags_upper_32_bits = SVGA3D_FLAGS_UPPER_32(flags);
region->data = NULL;
region->handle = rep->handle;
region->map_handle = rep->map_handle;
+ region->map_count = 0;
region->size = size;
region->drm_fd = vws->ioctl.drm_fd;
vmw_printf("%s: gmrId = %u, offset = %u\n", __FUNCTION__,
region->ptr.gmrId, region->ptr.offset);
- assert(region->data == NULL);
+ if (region->data) {
+ os_munmap(region->data, region->size);
+ region->data = NULL;
+ }
memset(&arg, 0, sizeof(arg));
arg.handle = region->handle;
region->data = map;
}
+ ++region->map_count;
+
return region->data;
}
vmw_printf("%s: gmrId = %u, offset = %u\n", __FUNCTION__,
region->ptr.gmrId, region->ptr.offset);
+ --region->map_count;
os_munmap(region->data, region->size);
region->data = NULL;
}
(version->version_major == 2 && version->version_minor > 15);
vws->ioctl.have_drm_2_17 = version->version_major > 2 ||
(version->version_major == 2 && version->version_minor > 16);
+ vws->ioctl.have_drm_2_18 = version->version_major > 2 ||
+ (version->version_major == 2 && version->version_minor > 17);
vws->ioctl.drm_execbuf_version = vws->ioctl.have_drm_2_9 ? 2 : 1;
}
}
+ if (vws->ioctl.have_drm_2_18 && vws->base.have_sm4_1) {
+ memset(&gp_arg, 0, sizeof(gp_arg));
+ gp_arg.param = DRM_VMW_PARAM_SM5;
+ ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
+ &gp_arg, sizeof(gp_arg));
+ if (ret == 0 && gp_arg.value != 0) {
+ vws->base.have_sm5 = TRUE;
+ }
+ }
+
memset(&gp_arg, 0, sizeof(gp_arg));
gp_arg.param = DRM_VMW_PARAM_3D_CAPS_SIZE;
ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
#define DRM_VMW_PARAM_DX 12
#define DRM_VMW_PARAM_HW_CAPS2 13
#define DRM_VMW_PARAM_SM4_1 14
+#define DRM_VMW_PARAM_SM5 15
/**
* enum drm_vmw_handle_type - handle type for ref ioctls
* @svga3d_flags_upper_32_bits: Upper 32 bits of svga3d flags.
* @multisample_pattern: Multisampling pattern when msaa is supported.
* @quality_level: Precision settings for each sample.
+ * @buffer_byte_stride: Buffer byte stride.
* @must_be_zero: Reserved for future usage.
*
* Input argument to the DRM_VMW_GB_SURFACE_CREATE_EXT Ioctl.
struct drm_vmw_gb_surface_create_ext_req {
struct drm_vmw_gb_surface_create_req base;
enum drm_vmw_surface_version version;
- uint32_t svga3d_flags_upper_32_bits;
- SVGA3dMSPattern multisample_pattern;
- SVGA3dMSQualityLevel quality_level;
- uint64_t must_be_zero;
+ __u32 svga3d_flags_upper_32_bits;
+ __u32 multisample_pattern;
+ __u32 quality_level;
+ __u32 buffer_byte_stride;
+ __u32 must_be_zero;
};
/**