Restrict a VSX extract to TARGET_POWERPC64 (PR88213)

This pattern optimises a scalar extract from a vector loaded from
memory to be just a scalar load from memory.  But to do a 64-bit
integer load you need 64-bit integer registers, which needs
TARGET_POWERPC64.

	PR target/88213
	* config/rs6000/vsx.md (*vsx_extract_<P:mode>_<VSX_D:mode>_load):
	Require TARGET_POWERPC64.

From-SVN: r267263

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 56e50e2cbfb8b89ee076f35e50b1ecc0fd4c6768..6fe6ec342c1f4dd1a806ff179e773a0b30dd92a8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-12-19  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       PR target/88213
+       * config/rs6000/vsx.md (*vsx_extract_<P:mode>_<VSX_D:mode>_load):
+       Require TARGET_POWERPC64.
+
 2018-12-19  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/88533

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 65a9892ff9ff89336fe043556503143be40304f4..38223a5736513fdef24f3f2ce458523b2c4fabcd 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3257,7 +3257,7 @@
         (match_operand:VSX_D 1 "memory_operand" "m,m")
         (parallel [(match_operand:QI 2 "const_0_to_1_operand" "n,n")])))
    (clobber (match_scratch:P 3 "=&b,&b"))]
-  "VECTOR_MEM_VSX_P (<VSX_D:MODE>mode)"
+  "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<VSX_D:MODE>mode)"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (match_dup 4))]