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verilog_parser: turn S/R and R/R conflicts into hard errors.
authorwhitequark <whitequark@whitequark.org>
Thu, 9 Jul 2020 19:36:39 +0000 (19:36 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 9 Jul 2020 19:36:59 +0000 (19:36 +0000)
Fixes #2253.

frontends/verilog/Makefile.inc patch | blob | history

diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index cf9b9531e49421533d848811e84e87228012b871..d5d5edd3d0e3022f05c3a5141301b89002181ba6 100644 (file)
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -6,7 +6,7 @@ GENFILES += frontends/verilog/verilog_lexer.cc
 
 frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
        $(Q) mkdir -p $(dir $@)
-       $(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
+       $(P) $(BISON) -Werror=conflicts-sr,error=conflicts-rr -o $@ -d -r all -b frontends/verilog/verilog_parser $<
 
 frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc