(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index f4bbfcc99b2b35dd3bcc5ed7bb4a2c3000d98a97..537e36feed91bf94be5456d16befa541c342daac 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -117,10 +117,9 @@ Vectorisation of the VSX Packed SIMD system makes no sense whatsoever,
 the sole exceptions potentially being any operations with 128-bit
 operands such as `vrlq` (Rotate Quad Word) and `xsaddqp` (Scalar
 Quad-precision Add).
-SV effectively *replaces* VSX requiring far less instructions, and provides,
-at the very minimum, predication (which VSX was designed without).
-Thus all VSX Major Opcodes - all of them - are "unused" and must raise
-illegal instruction exceptions in SV Prefix Mode.
+SV effectively *replaces* the majority of VSX, requiring far less 
+instructions, and provides, at the very minimum, predication
+(which VSX was designed without).
 
 Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to
 have because they are not only provided by SV, the SV alternatives may