targets/sim: switch from shadow_base to io_regions

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 9e4210b2599f05655c24a8ef86bfdd1a389a1aff..d8b148a4b88422876f352a24cf16f33f715bc5da 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -73,7 +73,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -86,7 +86,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index cfa9f438e3cae07829017ef8432163011de89cb2..9d2ef599b0c09c8f5b17aaeecae5aeeaa83c7a14 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -65,7 +65,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -78,7 +78,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index ba6aab5c88cce4bbc77fe2cf01b16bd834e1cf43..17d6a108ccc3f6782cdf48212c2eebf1b75fbaf9 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -67,7 +67,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -80,7 +80,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 0849396621ccc2fa99f6eab89fd976c4abf33255..ba3accd4e525295a1462d6e85c86051f75877a8e 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -117,7 +117,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 13137703b531bab9ff5ac5913d56882eadc5ce8b..9bfa6739798449e113a4b2b9074e612362bf1d45 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index e24e6fb99795958181777357aae9ede0cf616316..742e3342573650db634f3e2f218bdaf8c2dca13d 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -71,7 +71,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 73f2565a6d3e427dbb529d4652b0ef5d2ce5d8aa..06b656b107e114f836db8d02af27edc1c0e474f3 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -70,7 +70,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -83,7 +83,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index a1fce67035e4f65ffe31d12738de0b3a934b6e1e..b615a669c480757fdbb574a7580421d5c84c5eca 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -31,7 +31,7 @@ class BaseSoC(SoCCore):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -44,7 +44,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 4e673945256b0c96b3d9fa56006e5c6b34f6753f..bc9eacb1175325280ffd072d5d006ae1eb710e29 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -104,7 +104,7 @@ class BaseSoC(SoCSDRAM):
 
 class EthernetSoC(BaseSoC):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -118,7 +118,7 @@ class EthernetSoC(BaseSoC):
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
         self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index b0238ce12e4133f161b0922322b55a5efdf5d0c1..96fa6637eeb6ac67238544bd1b6cf90f006b4d63 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -88,7 +88,7 @@ class Platform(SimPlatform):
 
 class SimSoC(SoCSDRAM):
     mem_map = {
-        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+        "ethmac": 0xb0000000,
     }
     mem_map.update(SoCSDRAM.mem_map)
 
@@ -153,7 +153,7 @@ class SimSoC(SoCSDRAM):
                 ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx":  "ethphy_eth_rx"})(ethmac)
             self.submodules.ethmac = ethmac
             self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-            self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+            self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True)
             self.add_csr("ethmac")
             self.add_interrupt("ethmac")