Add test from #1144, and try reading without '-specify' flag

diff --git a/tests/various/specify.v b/tests/various/specify.v
index afc421da8a3eda3667a29534506d076550548301..b1f3992671801f374a0bbfd60562601862d1036e 100644 (file)
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -28,3 +28,17 @@ module test2 (
                (B => Q) = 1.5;
        endspecify
 endmodule
+
+module issue01144(input clk, d, output q);
+specify
+  // Fails:
+  (posedge clk => (q +: d)) = (3,1);
+  (/*posedge*/ clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+  (/*posedge*/ clk *> (q +: d)) = (3,1);
+
+  // Works:
+  (/*posedge*/ clk => q) = (3,1);
+  (/*posedge*/ clk *> q) = (3,1);
+endspecify
+endmodule

diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a5ca07219ae97055bdb573f8a04ae4256837d47a..a2b6038e47e81f95701e4a55c4aaa3ffb600acda 100644 (file)
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -54,3 +54,5 @@ equiv_struct
 equiv_induct -seq 5
 equiv_status -assert
 design -reset
+
+read_verilog specify.v