Set the ASI register to be something explicitly so that simulation is deterministic.
authorGabe Black <gblack@eecs.umich.edu>
Fri, 10 Nov 2006 09:14:25 +0000 (04:14 -0500)
committerGabe Black <gblack@eecs.umich.edu>
Fri, 10 Nov 2006 09:14:25 +0000 (04:14 -0500)
--HG--
extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99

src/arch/sparc/process.cc

index a3b7dde7c425a6656af4ff218760d6c29291774f..11a799ccbd4f8f980f26287cd0232e3cf408dc1b 100644 (file)
@@ -29,6 +29,7 @@
  *          Ali Saidi
  */
 
+#include "arch/sparc/asi.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/process.hh"
 #include "base/loader/object_file.hh"
@@ -105,6 +106,8 @@ SparcLiveProcess::startup()
     threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
     //Set the trap level to 0
     threadContexts[0]->setMiscReg(MISCREG_TL, 0);
+    //Set the ASI register to something fixed
+    threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
 }
 
 m5_auxv_t buildAuxVect(int64_t type, int64_t val)