gallium/radeon: use r600_gfx_write_event_eop everywhere
authorMarek Olšák <marek.olsak@amd.com>
Mon, 3 Oct 2016 13:37:19 +0000 (15:37 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 26 Oct 2016 11:02:58 +0000 (13:02 +0200)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeon/r600_pipe_common.c
src/gallium/drivers/radeon/r600_query.c
src/gallium/drivers/radeonsi/si_state_draw.c

index 835008360a6de253f34840fe1bb6ddbcbb67fc01..1a7a712beb2121de5fb50563ddb3e5ec58092e0b 100644 (file)
@@ -122,7 +122,9 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx,
        radeon_emit(cs, new_fence); /* immediate data */
        radeon_emit(cs, 0); /* unused */
 
-       r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
+       if (buf)
+               r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
+                               RADEON_PRIO_QUERY);
 }
 
 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
index ac71a4358e0ede71fa89f232a5b2ee6b84e0d494..a5c8595ea1233a0011da35adc34e6064daabb92b 100644 (file)
@@ -557,12 +557,8 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
                radeon_emit(cs, (va >> 32) & 0xFFFF);
                break;
        case PIPE_QUERY_TIME_ELAPSED:
-               radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-               radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
-               radeon_emit(cs, va);
-               radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
-               radeon_emit(cs, 0);
-               radeon_emit(cs, 0);
+               r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
+                                        0, 3, NULL, va, 0, 0);
                break;
        case PIPE_QUERY_PIPELINE_STATISTICS:
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
@@ -643,13 +639,8 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
                va += 8;
                /* fall through */
        case PIPE_QUERY_TIMESTAMP:
-               radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-               radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
-               radeon_emit(cs, va);
-               radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
-               radeon_emit(cs, 0);
-               radeon_emit(cs, 0);
-
+               r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
+                                        0, 3, NULL, va, 0, 0);
                fence_va = va + 8;
                break;
        case PIPE_QUERY_PIPELINE_STATISTICS: {
index d18137b66910c9885e9402a234861114a4e816fe..c0e2642ba3d2fb67857afeaeca137cfca2b9869f 100644 (file)
@@ -740,15 +740,9 @@ void si_emit_cache_flush(struct si_context *sctx)
                                 S_0085F0_CB7_DEST_BASE_ENA(1);
 
                /* Necessary for DCC */
-               if (rctx->chip_class >= VI) {
-                       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-                       radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
-                                       EVENT_INDEX(5));
-                       radeon_emit(cs, 0);
-                       radeon_emit(cs, 0);
-                       radeon_emit(cs, 0);
-                       radeon_emit(cs, 0);
-               }
+               if (rctx->chip_class == VI)
+                       r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
+                                                0, 0, NULL, 0, 0, 0);
        }
        if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
                cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |