+2017-01-10 Sandra Loosemore <sandra@codesourcery.com>
+
+ * doc/extend.texi: Tweak formatting to fix overfull hbox warnings.
+ * doc/invoke.texi: Likewise.
+ * doc/md.texi: Likewise.
+ * doc/objc.texi: Likewise.
+
2017-01-10 Joshua Conner <joshconner@google.com>
* config/arm/fuchsia-elf.h: New file.
@{ ...
@} > text
/* Leave .rodata in flash and add an offset of 0x4000 to all
- addresses so that respective objects can be accessed by LD
- instructions and open coded C/C++. This means there is no
- need for progmem in the source and no overhead by read-only
- data in RAM. */
+ addresses so that respective objects can be accessed by
+ LD instructions and open coded C/C++. This means there
+ is no need for progmem in the source and no overhead by
+ read-only data in RAM. */
.rodata ADDR(.text) + SIZEOF (.text) + 0x4000 :
@{
*(.rodata)
With no modifiers, this is what the output from the operands would be for the
@samp{att} and @samp{intel} dialects of assembler:
-@multitable {Operand} {masm=att} {OFFSET FLAT:.L2}
-@headitem Operand @tab masm=att @tab masm=intel
+@multitable {Operand} {$.L2} {OFFSET FLAT:.L2}
+@headitem Operand @tab @samp{att} @tab @samp{intel}
@item @code{%0}
@tab @code{%eax}
@tab @code{eax}
The table below shows the list of supported modifiers and their effects.
-@multitable {Modifier} {Print the opcode suffix for the size of th} {Operand} {masm=att} {masm=intel}
-@headitem Modifier @tab Description @tab Operand @tab @option{masm=att} @tab @option{masm=intel}
+@multitable {Modifier} {Print the opcode suffix for the size of th} {Operand} {@samp{att}} {@samp{intel}}
+@headitem Modifier @tab Description @tab Operand @tab @samp{att} @tab @samp{intel}
@item @code{z}
@tab Print the opcode suffix for the size of the current integer operand (one of @code{b}/@code{w}/@code{l}/@code{q}).
@tab @code{%z0}
If the address does not point to flash memory, return @code{-1}.
@smallexample
-unsigned char __builtin_avr_insert_bits (unsigned long map, unsigned char bits, unsigned char val)
+unsigned char __builtin_avr_insert_bits (unsigned long map,
+ unsigned char bits,
+ unsigned char val)
@end smallexample
@noindent
vec_extract_sig (__vector double source);
__vector float
-vec_insert_exp (__vector unsigned int significands, __vector unsigned int exponents);
+vec_insert_exp (__vector unsigned int significands,
+ __vector unsigned int exponents);
__vector double
vec_insert_exp (__vector unsigned long long int significands,
__vector unsigned long long int exponents);
-__vector int vec_test_data_class (__vector float source, unsigned int condition);
-__vector long long int vec_test_data_class (__vector double source, unsigned int condition);
+__vector int vec_test_data_class (__vector float source,
+ unsigned int condition);
+__vector long long int vec_test_data_class (__vector double source,
+ unsigned int condition);
@end smallexample
The @code{vec_extract_sig} and @code{vec_extract_exp} built-in
int, int);
@end smallexample
-The second argument to the @var{__builtin_crypto_vshasigmad} and
-@var{__builtin_crypto_vshasigmaw} builtin functions must be a constant
-integer that is 0 or 1. The third argument to these builtin functions
+The second argument to @var{__builtin_crypto_vshasigmad} and
+@var{__builtin_crypto_vshasigmaw} must be a constant
+integer that is 0 or 1. The third argument to these built-in functions
must be a constant integer in the range of 0 to 15.
If the ISA 3.0 instruction set additions
The following built-in functions are available when @option{-mtbm} is used.
Both of them generate the immediate form of the bextr machine instruction.
@smallexample
-unsigned int __builtin_ia32_bextri_u32 (unsigned int, const unsigned int);
-unsigned long long __builtin_ia32_bextri_u64 (unsigned long long, const unsigned long long);
+unsigned int __builtin_ia32_bextri_u32 (unsigned int,
+ const unsigned int);
+unsigned long long __builtin_ia32_bextri_u64 (unsigned long long,
+ const unsigned long long);
@end smallexample
The default @env{GCC_COLORS} is
@smallexample
-error=01;31:warning=01;35:note=01;36:range1=32:range2=34:locus=01:quote=01:\
-fixit-insert=32:fixit-delete=31:\
+error=01;31:warning=01;35:note=01;36:range1=32:range2=34:locus=01:\
+quote=01:fixit-insert=32:fixit-delete=31:\
diff-filename=01:diff-hunk=32:diff-delete=31:diff-insert=32
@end smallexample
@noindent
-Wimplicit-int @r{(C and Objective-C only)} @gol
-Wimplicit-function-declaration @r{(C and Objective-C only)} @gol
-Winit-self @r{(only for C++)} @gol
--Wlogical-not-parentheses
+-Wlogical-not-parentheses @gol
-Wmain @r{(only for C/ObjC and unless} @option{-ffreestanding}@r{)} @gol
-Wmaybe-uninitialized @gol
-Wmemset-elt-size @gol
AddressSanitizer is @code{halt_on_error=1}. This can be overridden through
setting the @code{halt_on_error} flag in the corresponding environment variable.
-Syntax without explicit @var{opts} parameter is deprecated. It is equivalent to
-@smallexample
--fsanitize-recover=undefined,float-cast-overflow,float-divide-by-zero,bounds-strict
-@end smallexample
-@noindent
-Similarly @option{-fno-sanitize-recover} is equivalent to
+Syntax without an explicit @var{opts} parameter is deprecated. It is
+equivalent to specifying an @var{opts} list of:
+
@smallexample
--fno-sanitize-recover=undefined,float-cast-overflow,float-divide-by-zero,bounds-strict
+undefined,float-cast-overflow,float-divide-by-zero,bounds-strict
@end smallexample
@item -fsanitize-address-use-after-scope
Altivec vector register
@item wa
-Any VSX register if the -mvsx option was used or NO_REGS.
+Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd},
@code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
numbering.
@smallexample
-asm ("xvadddp %x0,%x1,%x2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
+asm ("xvadddp %x0,%x1,%x2"
+ : "=wa" (v1)
+ : "wa" (v2), "wa" (v3));
@end smallexample
+@noindent
is correct, but:
@smallexample
-asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
+asm ("xvadddp %0,%1,%2"
+ : "=wa" (v1)
+ : "wa" (v2), "wa" (v3));
@end smallexample
+@noindent
is not correct.
If an instruction only takes Altivec registers, you do not want to use
@code{%x<n>}.
@smallexample
-asm ("xsaddqp %0,%1,%2" : "=v" (v1) : "v" (v2), "v" (v3));
+asm ("xsaddqp %0,%1,%2"
+ : "=v" (v1)
+ : "v" (v2), "v" (v3));
@end smallexample
+@noindent
is correct because the @code{xsaddqp} instruction only takes Altivec
registers, while:
@smallexample
-asm ("xsaddqp %x0,%x1,%x2" : "=v" (v1) : "v" (v2), "v" (v3));
+asm ("xsaddqp %x0,%x1,%x2"
+ : "=v" (v1)
+ : "v" (v2), "v" (v3));
@end smallexample
+@noindent
is incorrect.
@item wb
@sp 1
-@multitable @columnfractions .25 .75
+@multitable @columnfractions .60 .40
@item Objective-C type
@tab Compiler encoding
@item
@smallexample
int a __attribute__ ((vector_size (16)));
@end smallexample
-@tab @code{![16,16i]} (alignment would depend on the machine)
+@tab @code{![16,16i]} (alignment depends on the machine)
@end multitable
@sp 1
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