build.xilinx: Run `phys_opt_design` and generate timing report.

Makes the flow more similar to migen.

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 3d40e9be1e583fd1b8ef9b3be5c08aba4a51b09f..709f746d78bde5e54ef8d55393600d8490e87187 100644 (file)
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -147,6 +147,8 @@ class XilinxVivadoToolchain:
         tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
         tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
         tcl.append("route_design")
+        tcl.append("phys_opt_design")
+        tcl.append("report_timing_summary -no_header -no_detailed_paths")
         tcl.append("write_checkpoint -force {}_route.dcp".format(build_name))
         tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
         tcl.append("report_drc -file {}_drc.rpt".format(build_name))