Declare trap handlers as global symbols. (#87)

This allows them to be referenced by other files, such as a test environment
that lives in a separate compilation unit.

diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
index ba683cc6608e6d3b8bd28bfd6b3700d59d1861bf..647430b8daa5865b836cd8caf255b8f63b58a004 100644 (file)
--- a/isa/rv64mi/breakpoint.S
+++ b/isa/rv64mi/breakpoint.S
@@ -115,6 +115,8 @@ RVTEST_CODE_BEGIN
 2:
   TEST_PASSFAIL
 
+  .align 2
+  .global mtvec_handler
 mtvec_handler:
   # Only even-numbered tests should trap.
   andi t0, TESTNUM, 1

diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index a1b445f0df08c7b3b47ab9b9fe41d62f4e115d08..3bb7961596d095735ff1d3ec2233479fd43cf8de 100644 (file)
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -106,6 +106,7 @@ bad9:
   TEST_PASSFAIL
 
   .align 8
+  .global mtvec_handler
 mtvec_handler:
   j synchronous_exception
   j msip

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index 1e5ab6888bd889357dc733306c5d8d9e3a0573c9..2f4d96dea9dfcbd321d8e2fa7687e21084655119 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -92,6 +92,7 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 3
+  .global mtvec_handler
 mtvec_handler:
   csrr t0, mcause
   bne t0, s1, fail

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 292e298608b8816def05c98ff14a46c898811c4e..5a8edbeaaf5ff28fcd7acc3701a5bd6d73057811 100644 (file)
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -110,6 +110,7 @@ finish:
   TEST_PASSFAIL
 
   .align 2
+  .global stvec_handler
 stvec_handler:
   # Trapping on tests 10-12 is good news.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.

diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
index 783522c1ed76ba7a3ce32fe408aa86891d5e1e2c..fa1581fa00482f55e69327b024e546a8c09426ee 100644 (file)
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64si/dirty.S
@@ -74,6 +74,7 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 2
+  .global mtvec_handler
 mtvec_handler:
   csrr t0, mcause
   add t0, t0, -CAUSE_STORE_PAGE_FAULT

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index eb50f944fdbb187138ae94d23c298732b469e880..594345687a83fc1436ae7cfc3e02bdfe7780fbb0 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -110,6 +110,7 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 2
+  .global stvec_handler
 stvec_handler:
   # tests 2, 4, 5, and 6 should trap
   li a0, 2

diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index c2a6e49ef70a76db72f99db3b66f1dac89c5d134..d5a2de7a0852ed52ad1c89ccdd115af17040569a 100644 (file)
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -30,6 +30,7 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 2
+  .global stvec_handler
 stvec_handler:
   li t1, CAUSE_BREAKPOINT
   csrr t0, scause

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 82ba7c0cbc81619d46a9cf8ff4f555509047cfc4..cb97635bab7a70b8d26472bd72661858801a8768 100644 (file)
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -40,6 +40,7 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 2
+  .global stvec_handler
 stvec_handler:
   li t1, CAUSE_USER_ECALL
   csrr t0, scause