Wire with init on FF part, 1'bx on non-FF part

diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index fcec9dd8c341f41c3571d6d21a88203f66459858..81f71b5badb5069afb92b9a2cb0e7985048460b0 100644 (file)
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,4 +1,4 @@
-module test(input clk, input [3:0] bar, output [3:0] foo);
+module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
   reg [3:0] foo = 0;
   reg [3:0] last_bar = 0;
   reg [3:0] asdf = 4'b1xxx;
@@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
   always @(posedge clk)
     last_bar <= bar;
 
+  always @(posedge clk)
+    asdf[3] <= bar[3];
   always @*
     asdf[2:0] = 3'b111;