Fix a regression from #3035.

diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc
index 4ca5bcbb4bbb71cf2a43bf63eb1bb7c1c2826f83..c65108413918755627ff0ccdf67e095ce2b1ff31 100644 (file)
--- a/kernel/ffmerge.cc
+++ b/kernel/ffmerge.cc
@@ -157,7 +157,7 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pai
 }
 
 bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) {
-       ff = FfData();
+       ff = FfData(module, initvals, NEW_ID);
        sigmap->apply(sig);
 
        bool found = false;

diff --git a/tests/memories/trans_addr_enable.v b/tests/memories/trans_addr_enable.v
new file mode 100644 (file)
index 0000000..f366f41
--- /dev/null
+++ b/tests/memories/trans_addr_enable.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+reg [7:0] rra;
+
+always @(posedge clk) begin
+       if (we)
+               mem[addr] <= wd;
+
+       if (rae)
+               rra <= addr;
+end
+
+assign rd = mem[rra];
+
+endmodule