i965: use align1 access mode for instructions with execSize=1 in VS

All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c
in oglconform.

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f8a3044dd0a0b47fc4a87208b722c147e9ed363a..88131c432ec82ac48f4d3bd2c85ac7fcd06949bc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1727,6 +1727,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
 
    /* Setup MRF[1] with location/offset into const buffer */
    brw_push_insn_state(p);
+   brw_set_access_mode(p, BRW_ALIGN_1);
    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
    brw_set_mask_control(p, BRW_MASK_DISABLE);
    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
@@ -1774,6 +1775,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
 
    /* Setup MRF[1] with offset into const buffer */
    brw_push_insn_state(p);
+   brw_set_access_mode(p, BRW_ALIGN_1);
    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
    brw_set_mask_control(p, BRW_MASK_DISABLE);
    brw_set_predicate_control(p, BRW_PREDICATE_NONE);