Add examples/osu035

diff --git a/examples/osu035/.gitignore b/examples/osu035/.gitignore
new file mode 100644 (file)
index 0000000..3abf340
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+++ b/examples/osu035/.gitignore
@@ -0,0 +1,3 @@
+osu035_stdcells.lib
+example.yslog
+example.edif

diff --git a/examples/osu035/Makefile b/examples/osu035/Makefile
new file mode 100644 (file)
index 0000000..8d8e247
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+++ b/examples/osu035/Makefile
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+
+example.edif: example.ys example.v osu035_stdcells.lib
+       yosys -l example.yslog -q example.ys
+
+osu035_stdcells.lib:
+       rm -f osu035_stdcells.lib.part osu035_stdcells.lib
+       wget -O osu035_stdcells.lib.part https://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/ami035/signalstorm/osu035_stdcells.lib
+       mv osu035_stdcells.lib.part osu035_stdcells.lib
+
+clean:
+       rm -f osu035_stdcells.lib
+       rm -f example.yslog example.edif
+

diff --git a/examples/osu035/example.v b/examples/osu035/example.v
new file mode 100644 (file)
index 0000000..0f043e5
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+++ b/examples/osu035/example.v
@@ -0,0 +1,3 @@
+module top (input clk, input [7:0] a, b, output reg [15:0] c);
+  always @(posedge clk) c <= a * b;
+endmodule

diff --git a/examples/osu035/example.ys b/examples/osu035/example.ys
new file mode 100644 (file)
index 0000000..040f776
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+++ b/examples/osu035/example.ys
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+read_verilog example.v
+read_liberty -lib osu035_stdcells.lib
+
+synth -top top
+
+dfflibmap -liberty osu035_stdcells.lib
+abc -liberty osu035_stdcells.lib
+opt_clean
+
+stat -liberty osu035_stdcells.lib
+write_edif example.edif