i965: Use MOV, not OR for setting URB write channel enables on Gen8+.

On Broadwell, g0.5 contains the "Scratch Space Pointer"; using OR
puts some bits of that into "ignored" sections of our message header.

While this doesn't hurt, it's also not terribly /useful/.  Using MOV
is sufficient to set the only interesting bits in this part of the
message header.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index d0f574a4ccb7ff93edaa877aa6f2117347149a40..7ed5d2a4b8c22d678701855337602168a13a32bf 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
@@ -173,11 +173,8 @@ gen8_vec4_generator::generate_urb_write(vec4_instruction *ir, bool vs)
    if (!(ir->urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
       /* Enable Channel Masks in the URB_WRITE_OWORD message header */
       default_state.access_mode = BRW_ALIGN_1;
-      inst = OR(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5),
-                       BRW_REGISTER_TYPE_UD),
-                retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
-                brw_imm_ud(0xff00));
-      gen8_set_mask_control(inst, BRW_MASK_DISABLE);
+      MOV_RAW(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5),
+              brw_imm_ud(0xff00));
       default_state.access_mode = BRW_ALIGN_16;
    }