boards/targets/sim: update litedram

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 0d08311293ad6cbfa732f8b1cc57cae9829eb56d..39a4911160c0106e7bfb85f9163521a5ca670369 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -13,7 +13,7 @@ from litex.soc.cores import uart
 from litex.soc.integration.soc_core import mem_decoder
 
 from litedram.modules import PhySettings, IS42S16160
-from litedram.model import SDRAMPHYModel
+from litedram.phy.model import SDRAMPHYModel
 
 from liteeth.phy.model import LiteEthPHYModel
 from liteeth.core.mac import LiteEthMAC