{
struct si_screen *sscreen = (struct si_screen *)screen;
struct pipe_context *ctx;
+ uint64_t total_ram;
if (sscreen->debug_flags & DBG(CHECK_VM))
flags |= PIPE_CONTEXT_DEBUG;
/* Use asynchronous flushes only on amdgpu, since the radeon
* implementation for fence_server_sync is incomplete. */
- return threaded_context_create(ctx, &sscreen->pool_transfers, si_replace_buffer_storage,
- sscreen->info.is_amdgpu ? si_create_fence : NULL,
- &((struct si_context *)ctx)->tc);
+ struct pipe_context * tc = threaded_context_create(
+ ctx, &sscreen->pool_transfers, si_replace_buffer_storage,
+ sscreen->info.is_amdgpu ? si_create_fence : NULL,
+ &((struct si_context *)ctx)->tc);
+
+ if (os_get_total_physical_memory(&total_ram)) {
+ ((struct threaded_context *) tc)->bytes_mapped_limit = total_ram / 4;
+ }
+
+ return tc;
}
/*