soc: Don't create a share intercon with only one master and one slave

This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index b2e492968de1ad961d3121ba8b8551829ab8e699..42366b6c1042f7552d3959c6208a9ac5ce3ef82a 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -824,7 +824,14 @@ class SoC(Module):
         # SoC Bus Interconnect ---------------------------------------------------------------------
         bus_masters = self.bus.masters.values()
         bus_slaves  = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()]
-        if len(bus_masters) and len(bus_slaves):
+        # One master and one slave, use a point to point interconnect, this is useful for
+        # generating standalone components such as LiteDRAM whose external control
+        # interface is a wishbone.
+        if len(bus_masters) == 1 and len(bus_slaves) == 1:
+            self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint(
+                master = list(bus_masters)[0],
+                slave  = list(self.bus.slaves.values())[0])
+        elif len(bus_masters) and len(bus_slaves):
             self.submodules.bus_interconnect = wishbone.InterconnectShared(
                 masters        = bus_masters,
                 slaves         = bus_slaves,