temporarily revert opcode changes

b9ffa13 isatables/minor_22.csv: reflect a new XO bit
0e87485 power_decoder: reflect a new XO bit
e5564ad svp64.py: sync remap opcode
c968dab svp64.py: sync svshape opcode

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index 591a6019707303d6044ca0e5c086eea2601c07b9..9fc38e024d34b62e4a715dc4299ea9436fdbc4fa 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -1,5 +1,5 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
-0b000000,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b000001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b000010,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0b000011,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0b00000,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0b00001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svshape,SVM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0b00010,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svremap,SVRM,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+0b00011,VL,OP_SVSTEP,NONE,NONE,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svstep,SVL,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index ae4cf67640c09653d291cc5774387dc3bc6e5d10..39ba5f22a46c35ed3824faacb9bad8c96d43f396 100644 (file)
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -735,7 +735,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
         Subdecoder(pattern=62, opcodes=get_csv("minor_62.csv"),
                    opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]),
         Subdecoder(pattern=22, opcodes=get_csv("minor_22.csv"),
-                   opint=True, bitsel=(0, 5), suffix=None, subdecoders=[]),
+                   opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]),
         Subdecoder(pattern=5, opcodes=get_csv("minor_5.csv"),
                    opint=True, bitsel=(0, 11), suffix=None, subdecoders=[]),
     ]

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index a2745dbac05b331885627fc9cac23e7d25a752be..cebf32e41f39c706b0b7cb32fa53f72480a66884 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -243,16 +243,16 @@ class SVP64Asm:
         # and svshape.  note that the dimension fields one subtracted from each
         if opcode == 'svshape':
             # 1.6.33 SVM-FORM from fields.txt
-            # |0     |6        |11      |16    |21    |25 |26    |31  |
-            # | PO   |  SVxd   |   SVyd | SVzd | SVRM |vf |   XO      |
+            # |0  |6        |11      |16    |21    |25 |26    |31  |
+            # |PO |  SVxd   |   SVyd | SVzd | SVRM |vf |   XO |  / |
             insn = 22 << (31-5)          # opcode 22, bits 0-5
             fields = list(map(int, fields))
             insn |= (fields[0]-1) << (31-10)  # SVxd       , bits 6-10
             insn |= (fields[1]-1) << (31-15)  # SVyd       , bits 11-15
             insn |= (fields[2]-1) << (31-20)  # SVzd       , bits 16-20
-            insn |= (fields[3]) << (31-24)    # SVRM       , bits 21-24
-            insn |= (fields[4]) << (31-25)    # vf         , bits 25
-            insn |= 0b00001 << (31-31)        # XO         , bits 26..31
+            insn |= (fields[3]) << (31-24)  # SVRM       , bits 21-24
+            insn |= (fields[4]) << (31-25)  # vf         , bits 25
+            insn |= 0b00001 << (31-30)  # XO       , bits 26..30
             #insn &= ((1<<32)-1)
             log("svshape", bin(insn))
             yield ".long 0x%x" % insn
@@ -267,7 +267,7 @@ class SVP64Asm:
         if opcode == 'svremap':
             # 1.6.34 SVRM-FORM from fields.txt
             # |0  |6     |11  |13   |15   |17   |19   |21  |22   |26     |31 |
-            # |PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO        |
+            # |PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO    | / |
             insn = 22 << (31-5)          # opcode 22, bits 0-5
             fields = list(map(int, fields))
             insn |= fields[0] << (31-10)  # SVme       , bits 6-10
@@ -277,7 +277,7 @@ class SVP64Asm:
             insn |= fields[4] << (31-18)  # m00        , bits 17-18
             insn |= fields[5] << (31-20)  # m01        , bits 19-20
             insn |= fields[6] << (31-21)  # pst        , bit 21
-            insn |= 0b00010 << (31-31)    # XO         , bits 26..30
+            insn |= 0b00010 << (31-30)  # XO       , bits 26..30
             #insn &= ((1<<32)-1)
             log("svremap", bin(insn))
             yield ".long 0x%x" % insn