x86: tighten assertion in build_modrm_byte()

All VEX3SOURCES cases should have VexW set, and all should have a SIMD
register destination.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 057a45fb0fb03f08d5b88b4d3d922b44c9c68df8..7cd0a106b3919f11150bc3cf66069efe98c97de5 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-04-26  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (build_modrm_byte): Extend assertion in
+       vex_3_sources handling to cover more cases.
+
 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (build_modrm_byte): Drop code dealing with

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 014720ea3c2c5876c893289c7c0eee35d62952dc..7126ca47fd175af07f390c08266e192d4f614c2d 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6591,10 +6591,9 @@ build_modrm_byte (void)
                   && i.tm.opcode_modifier.vexvvvv == VEXXDS
                   && (i.tm.opcode_modifier.veximmext
                       || (i.imm_operands == 1
-                          && i.types[0].bitfield.vec_imm4
-                          && (i.tm.opcode_modifier.vexw == VEXW0
-                              || i.tm.opcode_modifier.vexw == VEXW1)
-                          && i.tm.operand_types[dest].bitfield.regsimd)));
+                         && i.types[0].bitfield.vec_imm4))
+                 && i.tm.opcode_modifier.vexw
+                 && i.tm.operand_types[dest].bitfield.regsimd);
 
       if (i.imm_operands == 0)
         {