adapt LiteEth to new SoC

diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py
index dcc8bb4c5d11d01d4158b7c1faaae5ad99aea63f..6f504bb21a86ebc6c903ff7b4620350fbfada244 100644 (file)
--- a/misoclib/com/liteeth/example_designs/make.py
+++ b/misoclib/com/liteeth/example_designs/make.py
@@ -72,6 +72,8 @@ if __name__ == "__main__":
        top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
        soc = top_class(platform, **top_kwargs)
        soc.finalize()
+       memory_regions = soc.get_memory_regions()
+       csr_regions = soc.get_csr_regions()
 
        # decode actions
        action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
@@ -121,7 +123,7 @@ System Clk: {} MHz
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.csr_regions)
+               csr_csv = cpuif.get_csr_csv(csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]:

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index 3c2a120f8f4b234ff04132d1a4c2d6bd184debb9..f1d95dd72b5a2f7c2c660485a6eb8d360278684f 100644 (file)
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -23,14 +23,15 @@ class BaseSoC(SoC, AutoCSR):
                        mac_address=0x10e2d5000000,
                        ip_address="192.168.0.42"):
                clk_freq = int((1/(platform.default_clk_period))*1000000000)
-               self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
-               SoC.__init__(self, platform, clk_freq, self.uart2wb,
-                       with_cpu=False,
+               SoC.__init__(self, platform, clk_freq,
+                       cpu_type="none",
                        with_csr=True, csr_data_width=32,
                        with_uart=False,
                        with_identifier=True,
                        with_timer=False
                )
+               self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
+               self.add_wb_master(self.cpu_or_bridge.wishbone)
                self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
                # wishbone SRAM (to test Wishbone over UART and Etherbone)