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re PR target/84422 (ICE on various builtin test functions when compiled with -mcpu...
authorCarl Love <carll@gcc.gnu.org>
Wed, 14 Mar 2018 23:01:12 +0000 (23:01 +0000)
committerCarl Love <carll@gcc.gnu.org>
Wed, 14 Mar 2018 23:01:12 +0000 (23:01 +0000)
gcc/ChangeLog:

2018-03-14  Carl Love  <cel@us.ibm.com>

PR target/84422
* config/rs6000/rs6000-builtin.def: Change expansion for
VMULESW to BU_P8V_AV_2.
Change expansion for VMULEUW to BU_P8V_AV_2.
* config/rs6000/rs6000.c: Change
ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW.
Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW.
Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW.
Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW.
* config/rs6000/rs6000-c.c: Change
ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW.
Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW.
Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW.
Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW.

From-SVN: r258539

gcc/config/rs6000/rs6000-builtin.def patch | blob | history
gcc/config/rs6000/rs6000-c.c patch | blob | history
gcc/config/rs6000/rs6000.c patch | blob | history

diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 1efa8b600e8bd03299f0564fa295cf3cb7e3bd8f..44c86de8b1b169f6005338409b5da38cbfd54e60 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1086,14 +1086,14 @@ BU_ALTIVEC_2 (VMULEUB,        "vmuleub",        CONST,  vec_widen_umult_even_v16qi)
 BU_ALTIVEC_2 (VMULESB,       "vmulesb",        CONST,  vec_widen_smult_even_v16qi)
 BU_ALTIVEC_2 (VMULEUH,       "vmuleuh",        CONST,  vec_widen_umult_even_v8hi)
 BU_ALTIVEC_2 (VMULESH,       "vmulesh",        CONST,  vec_widen_smult_even_v8hi)
-BU_ALTIVEC_2 (VMULEUW,       "vmuleuw",        CONST,  vec_widen_umult_even_v4si)
-BU_ALTIVEC_2 (VMULESW,       "vmulesw",        CONST,  vec_widen_smult_even_v4si)
+BU_P8V_AV_2 (VMULEUW,        "vmuleuw",        CONST,  vec_widen_umult_even_v4si)
+BU_P8V_AV_2 (VMULESW,        "vmulesw",        CONST,  vec_widen_smult_even_v4si)
 BU_ALTIVEC_2 (VMULOUB,       "vmuloub",        CONST,  vec_widen_umult_odd_v16qi)
 BU_ALTIVEC_2 (VMULOSB,       "vmulosb",        CONST,  vec_widen_smult_odd_v16qi)
 BU_ALTIVEC_2 (VMULOUH,       "vmulouh",        CONST,  vec_widen_umult_odd_v8hi)
 BU_ALTIVEC_2 (VMULOSH,       "vmulosh",        CONST,  vec_widen_smult_odd_v8hi)
-BU_ALTIVEC_2 (VMULOUW,       "vmulouw",        CONST,  vec_widen_umult_odd_v4si)
-BU_ALTIVEC_2 (VMULOSW,       "vmulosw",        CONST,  vec_widen_smult_odd_v4si)
+BU_P8V_AV_2 (VMULOUW,        "vmulouw",        CONST,  vec_widen_umult_odd_v4si)
+BU_P8V_AV_2 (VMULOSW,        "vmulosw",        CONST,  vec_widen_smult_odd_v4si)
 BU_ALTIVEC_2 (VNOR,          "vnor",           CONST,  norv4si3)
 BU_ALTIVEC_2 (VOR,           "vor",            CONST,  iorv4si3)
 BU_ALTIVEC_2 (VPKUHUM,       "vpkuhum",        CONST,  altivec_vpkuhum)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 9ffb253816d06618d9d888275591335d7900a7ff..7fcb334724b81e45707ccd7432d02113be1dde09 100644 (file)
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2231,9 +2231,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW,
+  { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW,
+  { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
     RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
@@ -2244,9 +2244,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VMULEUW, ALTIVEC_BUILTIN_VMULEUW,
+  { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VMULESW, ALTIVEC_BUILTIN_VMULESW,
+  { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
@@ -2254,9 +2254,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSW,
+  { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUW,
+  { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
     RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
@@ -2269,9 +2269,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VMULOUW, ALTIVEC_BUILTIN_VMULOUW,
+  { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VMULOSW, ALTIVEC_BUILTIN_VMULOSW,
+  { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 
   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7e3e5a637f5ec35520e87d3b9588ebb736d28f8e..f8120a2180933c84a7e19d036e75fae99b8463cf 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16264,11 +16264,11 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
     /* Even element flavors of vec_mul (signed). */
     case ALTIVEC_BUILTIN_VMULESB:
     case ALTIVEC_BUILTIN_VMULESH:
-    case ALTIVEC_BUILTIN_VMULESW:
+    case P8V_BUILTIN_VMULESW:
     /* Even element flavors of vec_mul (unsigned).  */
     case ALTIVEC_BUILTIN_VMULEUB:
     case ALTIVEC_BUILTIN_VMULEUH:
-    case ALTIVEC_BUILTIN_VMULEUW:
+    case P8V_BUILTIN_VMULEUW:
       arg0 = gimple_call_arg (stmt, 0);
       arg1 = gimple_call_arg (stmt, 1);
       lhs = gimple_call_lhs (stmt);
@@ -16279,11 +16279,11 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
     /* Odd element flavors of vec_mul (signed).  */
     case ALTIVEC_BUILTIN_VMULOSB:
     case ALTIVEC_BUILTIN_VMULOSH:
-    case ALTIVEC_BUILTIN_VMULOSW:
+    case P8V_BUILTIN_VMULOSW:
     /* Odd element flavors of vec_mul (unsigned). */
     case ALTIVEC_BUILTIN_VMULOUB:
     case ALTIVEC_BUILTIN_VMULOUH:
-    case ALTIVEC_BUILTIN_VMULOUW:
+    case P8V_BUILTIN_VMULOUW:
       arg0 = gimple_call_arg (stmt, 0);
       arg1 = gimple_call_arg (stmt, 1);
       lhs = gimple_call_lhs (stmt);
@@ -18155,10 +18155,10 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
     /* unsigned 2 argument functions.  */
     case ALTIVEC_BUILTIN_VMULEUB:
     case ALTIVEC_BUILTIN_VMULEUH:
-    case ALTIVEC_BUILTIN_VMULEUW:
+    case P8V_BUILTIN_VMULEUW:
     case ALTIVEC_BUILTIN_VMULOUB:
     case ALTIVEC_BUILTIN_VMULOUH:
-    case ALTIVEC_BUILTIN_VMULOUW:
+    case P8V_BUILTIN_VMULOUW:
     case CRYPTO_BUILTIN_VCIPHER:
     case CRYPTO_BUILTIN_VCIPHERLAST:
     case CRYPTO_BUILTIN_VNCIPHER: