Added cell->known(), cell->input(portname), cell->output(portname)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8c64217bb180a67e8069bfad4cd4041a3770a938..b1e2c0e8ed5a9daa1a6919fe0ed92b1f120bbf54 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -19,6 +19,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/macc.h"
+#include "kernel/celltypes.h"
 #include "frontends/verilog/verilog_frontend.h"
 #include "backends/ilang/ilang_backend.h"
 
@@ -1928,6 +1929,39 @@ const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
        return connections_;
 }
 
+bool RTLIL::Cell::known() const
+{
+       if (yosys_celltypes.cell_known(type))
+               return true;
+       if (module && module->design && module->design->module(type))
+               return true;
+       return false;
+}
+
+bool RTLIL::Cell::input(RTLIL::IdString portname) const
+{
+       if (yosys_celltypes.cell_known(type))
+               return yosys_celltypes.cell_input(type, portname);
+       if (module && module->design) {
+               RTLIL::Module *m = module->design->module(type);
+               RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
+               return w && w->port_input;
+       }
+       return false;
+}
+
+bool RTLIL::Cell::output(RTLIL::IdString portname) const
+{
+       if (yosys_celltypes.cell_known(type))
+               return yosys_celltypes.cell_output(type, portname);
+       if (module && module->design) {
+               RTLIL::Module *m = module->design->module(type);
+               RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
+               return w && w->port_output;
+       }
+       return false;
+}
+
 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
 {
        return parameters.count(paramname) != 0;

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c17ede3d0a5b0342837e79da12487511578e4044..985bffe5e58532bc37207c1633c37bb57ff42ff8 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1140,6 +1140,11 @@ public:
        const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
        const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
 
+       // information about cell ports
+       bool known() const;
+       bool input(RTLIL::IdString portname) const;
+       bool output(RTLIL::IdString portname) const;
+
        // access cell parameters
        bool hasParam(RTLIL::IdString paramname) const;
        void unsetParam(RTLIL::IdString paramname);