Fix a ghdlsynth issue in icache

ghdlsynth doesn't like the debug statement, so wrap it in a generate.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/core.vhdl b/core.vhdl
index f4fe302682140e2b6fbf8e3f40848037812d3e87..eb0b526d9f4d082b2cacfab753e136ab4bcdab74 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -143,6 +143,7 @@ begin
 
     icache_0: entity work.icache
         generic map(
+            SIM => SIM,
             LINE_SIZE => 64,
             NUM_LINES => 32,
            NUM_WAYS => 2

diff --git a/icache.vhdl b/icache.vhdl
index 20d57240ce6bfc37e815521b8d2ce16930bf52dd..343c73a358a027bcb7e55540f1e8cd8cc949c5b3 100644 (file)
--- a/icache.vhdl
+++ b/icache.vhdl
@@ -29,6 +29,7 @@ use work.wishbone_types.all;
 
 entity icache is
     generic (
+        SIM : boolean := false;
         -- Line size in bytes
         LINE_SIZE : positive := 64;
         -- Number of lines in a set
@@ -264,6 +265,7 @@ begin
     assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
        report "geometry bits don't add up" severity FAILURE;
 
+    sim_debug: if SIM generate
     debug: process
     begin
        report "ROW_SIZE      = " & natural'image(ROW_SIZE);
@@ -280,6 +282,7 @@ begin
        report "WAY_BITS      = " & natural'image(WAY_BITS);
        wait;
     end process;
+    end generate;
 
     -- Generate a cache RAM for each way
     rams: for i in 0 to NUM_WAYS-1 generate