extern bool riscv_split_64bit_move_p (rtx, rtx);
extern void riscv_split_doubleword_move (rtx, rtx);
extern const char *riscv_output_move (rtx, rtx);
-extern const char *riscv_output_gpr_save (unsigned);
extern const char *riscv_output_return ();
#ifdef RTX_CODE
extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
&& GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC_VOLATILE
&& (GET_CODE (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0))
== CONST_INT)
- && INTVAL (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0)) == 2)
+ && INTVAL (XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 0)) == 0)
return insn;
return NULL;
RTX_FRAME_RELATED_P (insn) = 1;
}
-/* Return the code to invoke the GPR save routine. */
-
-const char *
-riscv_output_gpr_save (unsigned mask)
-{
- static char s[32];
- unsigned n = riscv_save_libcall_count (mask);
-
- ssize_t bytes = snprintf (s, sizeof (s), "call\tt0,__riscv_save_%u", n);
- gcc_assert ((size_t) bytes < sizeof (s));
-
- return s;
-}
-
/* For stack frames that can't be allocated with a single ADDI instruction,
compute the best value to initially allocate. It must at a minimum
allocate enough space to spill the callee-saved registers. If TARGET_RVC,
RTVEC_ELT (vec, 0) =
gen_rtx_UNSPEC_VOLATILE (VOIDmode,
- gen_rtvec (1, GEN_INT (frame->mask)), UNSPECV_GPR_SAVE);
+ gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE);
for (int i = 1; i < veclen; ++i)
{
[(unspec_volatile [(match_operand 0 "const_int_operand")]
UNSPECV_GPR_SAVE)])]
""
- { return riscv_output_gpr_save (INTVAL (operands[0])); })
+ "call\tt0,__riscv_save_%0")
(define_insn "gpr_restore"
[(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_RESTORE)]