[fix] Slave interface HP0 clk name

diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py
index a5451b25136f0686b0b963748140b7a207fcef57..4758cccbbb977ee93a90efa192cc7f443e06f366 100644 (file)
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@@ -142,7 +142,7 @@ class SoCZynq(SoCCore):
         self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
         self.ps7_params.update(
             # axi hp0 clk
-            i_M_AXI_HP0_ACLK=ClockSignal("sys"),
+            i_S_AXI_HP0_ACLK=ClockSignal("sys"),
 
             # axi hp0 aw
             i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,