radv: Translate logic ops.

radeonsi could pass them through but the enum changed between
Gallium and Vulkan, so we have to translate.

In progress I made the register defines a bit more readable.

CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 3588d39d62b44cb1619a306afb4001a4ba4fff86..e922b38ae3a10aee30c8ce7c815f62e043e7be3c 100644 (file)
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -6892,34 +6892,22 @@
 #define   S_028808_ROP3(x)                                            (((unsigned)(x) & 0xFF) << 16)
 #define   G_028808_ROP3(x)                                            (((x) >> 16) & 0xFF)
 #define   C_028808_ROP3                                               0xFF00FFFF
-#define     V_028808_X_0X00                                         0x00
-#define     V_028808_X_0X05                                         0x05
-#define     V_028808_X_0X0A                                         0x0A
-#define     V_028808_X_0X0F                                         0x0F
-#define     V_028808_X_0X11                                         0x11
-#define     V_028808_X_0X22                                         0x22
-#define     V_028808_X_0X33                                         0x33
-#define     V_028808_X_0X44                                         0x44
-#define     V_028808_X_0X50                                         0x50
-#define     V_028808_X_0X55                                         0x55
-#define     V_028808_X_0X5A                                         0x5A
-#define     V_028808_X_0X5F                                         0x5F
-#define     V_028808_X_0X66                                         0x66
-#define     V_028808_X_0X77                                         0x77
-#define     V_028808_X_0X88                                         0x88
-#define     V_028808_X_0X99                                         0x99
-#define     V_028808_X_0XA0                                         0xA0
-#define     V_028808_X_0XA5                                         0xA5
-#define     V_028808_X_0XAA                                         0xAA
-#define     V_028808_X_0XAF                                         0xAF
-#define     V_028808_X_0XBB                                         0xBB
-#define     V_028808_X_0XCC                                         0xCC
-#define     V_028808_X_0XDD                                         0xDD
-#define     V_028808_X_0XEE                                         0xEE
-#define     V_028808_X_0XF0                                         0xF0
-#define     V_028808_X_0XF5                                         0xF5
-#define     V_028808_X_0XFA                                         0xFA
-#define     V_028808_X_0XFF                                         0xFF
+#define     V_028808_ROP3_CLEAR                                     0x00
+#define     V_028808_ROP3_NOR                                       0x11
+#define     V_028808_ROP3_AND_INVERTED                              0x22
+#define     V_028808_ROP3_COPY_INVERTED                             0x33
+#define     V_028808_ROP3_AND_REVERSE                               0x44
+#define     V_028808_ROP3_INVERT                                    0x55
+#define     V_028808_ROP3_XOR                                       0x66
+#define     V_028808_ROP3_NAND                                      0x77
+#define     V_028808_ROP3_AND                                       0x88
+#define     V_028808_ROP3_EQUIVALENT                                0x99
+#define     V_028808_ROP3_NO_OP                                     0xaa
+#define     V_028808_ROP3_OR_INVERTED                               0xbb
+#define     V_028808_ROP3_COPY                                      0xcc
+#define     V_028808_ROP3_OR_REVERSE                                0xdd
+#define     V_028808_ROP3_OR                                        0xee
+#define     V_028808_ROP3_SET                                       0xff
 #define R_02880C_DB_SHADER_CONTROL                                      0x02880C
 #define   S_02880C_Z_EXPORT_ENABLE(x)                                 (((unsigned)(x) & 0x1) << 0)
 #define   G_02880C_Z_EXPORT_ENABLE(x)                                 (((x) >> 0) & 0x1)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 3d242e05bfd1a29f6f14ccede4b62d5cde484c8e..7a577dae413a58708f4a247480820fbedcd61c80 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -181,6 +181,47 @@ radv_pipeline_scratch_init(struct radv_device *device,
        return VK_SUCCESS;
 }
 
+static uint32_t si_translate_blend_logic_op(VkLogicOp op)
+{
+       switch (op) {
+       case VK_LOGIC_OP_CLEAR:
+               return V_028808_ROP3_CLEAR;
+       case VK_LOGIC_OP_AND:
+               return V_028808_ROP3_AND;
+       case VK_LOGIC_OP_AND_REVERSE:
+               return V_028808_ROP3_AND_REVERSE;
+       case VK_LOGIC_OP_COPY:
+               return V_028808_ROP3_COPY;
+       case VK_LOGIC_OP_AND_INVERTED:
+               return V_028808_ROP3_AND_INVERTED;
+       case VK_LOGIC_OP_NO_OP:
+               return V_028808_ROP3_NO_OP;
+       case VK_LOGIC_OP_XOR:
+               return V_028808_ROP3_XOR;
+       case VK_LOGIC_OP_OR:
+               return V_028808_ROP3_OR;
+       case VK_LOGIC_OP_NOR:
+               return V_028808_ROP3_NOR;
+       case VK_LOGIC_OP_EQUIVALENT:
+               return V_028808_ROP3_EQUIVALENT;
+       case VK_LOGIC_OP_INVERT:
+               return V_028808_ROP3_INVERT;
+       case VK_LOGIC_OP_OR_REVERSE:
+               return V_028808_ROP3_OR_REVERSE;
+       case VK_LOGIC_OP_COPY_INVERTED:
+               return V_028808_ROP3_COPY_INVERTED;
+       case VK_LOGIC_OP_OR_INVERTED:
+               return V_028808_ROP3_OR_INVERTED;
+       case VK_LOGIC_OP_NAND:
+               return V_028808_ROP3_NAND;
+       case VK_LOGIC_OP_SET:
+               return V_028808_ROP3_SET;
+       default:
+               unreachable("Unhandled logic op");
+       }
+}
+
+
 static uint32_t si_translate_blend_function(VkBlendOp op)
 {
        switch (op) {
@@ -600,9 +641,9 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
        }
        blend.cb_color_control = 0;
        if (vkblend->logicOpEnable)
-               blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
+               blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
        else
-               blend.cb_color_control |= S_028808_ROP3(0xcc);
+               blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
 
        blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
                S_028B70_ALPHA_TO_MASK_OFFSET1(2) |