st/glsl_to_nir: skip forced array splitting for tcs

nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 36adf55cd45c7438cc699399f3d124b8c1045a5a..7357eebae0cbb0015b5dd77e803ea607ee3abff1 100644 (file)
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -642,7 +642,8 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog,
 
    NIR_PASS_V(nir, nir_split_var_copies);
    NIR_PASS_V(nir, nir_lower_var_copies);
-   NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
+   if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+      NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
 
    if (nir->info.stage == MESA_SHADER_VERTEX) {
       /* Needs special handling so drvloc matches the vbo state: */