* Firstly: that instructions will never be ambiguously-defined.
* Secondly, that no instruction shall change meaning to produce
- different results on different hardware (present or future)
-* Thirdly, that implementors are not permitted to either add
+ different results on different hardware (present or future).
+* Thirdly, that Scalar "defined words" (32 bit instruction
+ encodings) if Vwctorised will also always be implemented as
+ identical Scalar instructions (the sole semi-exception being
+ Vevtorised Branch-Conditional)
+* Fourthly, that implementors are not permitted to either add
arbitrary features nor implement features in an incompatible
way. *(Performance may differ, but differing results are
not permitted)*.
-* Fourthly, that any part of Simple-V not implemented by
+* Fifthly, that any part of Simple-V not implemented by
a lower Compliancy Level is *required* to raise an illegal
- instruction trap (allowing soft-emulation).
-* Fifthly, that any `UNDEFINED` behaviour for practical implementation
+ instruction trap (allowing soft-emulation), including if
+ Simple-V is not implemented at all.
+* Sixthly, that any `UNDEFINED` behaviour for practical implementation
reasons is clearly documented for both programmers and hardware
implementors.