arch-gcn3: Fix sign extension for branches with multiplied offset

Certain branch instructions specify that the result of (simm16 * 4)
gets sign-extended before being added to the PC.

Previously, that result was being sign extended as if it was still a
16-bit number. This patch fixes that by having the result be sign
extended as an 18-bit number.

Change-Id: Id4d430f8daa71ca7910b570e7e39790626f1decf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41053
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc
index 03b11ab4887da7937f1234faa4d66ee5be5997e1..29de1a8a95162686ab4e9b69e8f4c5ebde409613 100644 (file)
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -3900,7 +3900,7 @@ namespace Gcn3ISA
         Addr pc = wf->pc();
         ScalarRegI16 simm16 = instData.SIMM16;
 
-        pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
+        pc = pc + ((ScalarRegI64)sext<18>(simm16 * 4LL)) + 4LL;
 
         wf->pc(pc);
     }
@@ -3946,7 +3946,7 @@ namespace Gcn3ISA
         scc.read();
 
         if (!scc.rawData()) {
-            pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
+            pc = pc + ((ScalarRegI64)sext<18>(simm16 * 4LL)) + 4LL;
         }
 
         wf->pc(pc);
@@ -3975,7 +3975,7 @@ namespace Gcn3ISA
         scc.read();
 
         if (scc.rawData()) {
-            pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
+            pc = pc + ((ScalarRegI64)sext<18>(simm16 * 4LL)) + 4LL;
         }
 
         wf->pc(pc);
@@ -4005,7 +4005,7 @@ namespace Gcn3ISA
         vcc.read();
 
         if (!vcc.rawData()) {
-            pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
+            pc = pc + ((ScalarRegI64)sext<18>(simm16 * 4LL)) + 4LL;
         }
 
         wf->pc(pc);
@@ -4035,7 +4035,7 @@ namespace Gcn3ISA
         if (vcc.rawData()) {
             Addr pc = wf->pc();
             ScalarRegI16 simm16 = instData.SIMM16;
-            pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
+            pc = pc + ((ScalarRegI64)sext<18>(simm16 * 4LL)) + 4LL;
             wf->pc(pc);
         }
     }
@@ -4060,7 +4060,7 @@ namespace Gcn3ISA
         if (wf->execMask().none()) {
             Addr pc = wf->pc();
             ScalarRegI16 simm16 = instData.SIMM16;
-            pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
+            pc = pc + ((ScalarRegI64)sext<18>(simm16 * 4LL)) + 4LL;
             wf->pc(pc);
         }
     }
@@ -4085,7 +4085,7 @@ namespace Gcn3ISA
         if (wf->execMask().any()) {
             Addr pc = wf->pc();
             ScalarRegI16 simm16 = instData.SIMM16;
-            pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
+            pc = pc + ((ScalarRegI64)sext<18>(simm16 * 4LL)) + 4LL;
             wf->pc(pc);
         }
     }