Add ice40_opt test

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
new file mode 100644 (file)
index 0000000..18e0d2b
--- /dev/null
+++ b/tests/ice40/ice40_opt.ys
@@ -0,0 +1,24 @@
+read_verilog -icells -formal <<EOT
+module top(input CI, I0, output CO, O);
+    wire A = 1'b0, B = 1'b0;
+       \$__ICE40_CARRY_WRAPPER #(
+               //    A[0]: 1010 1010 1010 1010
+               //    A[1]: 1100 1100 1100 1100
+               //    A[2]: 1111 0000 1111 0000
+               //    A[3]: 1111 1111 0000 0000
+               .LUT(~16'b 0110_1001_1001_0110)
+       ) fadd (
+               .A(A),
+               .B(B),
+               .CI(CI),
+               .I0(I0),
+               .I3(CI),
+               .CO(CO),
+               .O(O)
+       );
+endmodule
+EOT
+
+equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+design -load postopt
+select -assert-count 1 t:$lut