--- /dev/null
+logger -expect error "syntax error, unexpected TOK_CONSTVAL" 1
+read_verilog <<EOT
+module inverter(input a, output y);
+
+ assign y = (a == 1'b0? 1'b1 : 1'b0);
+
+endmodule // inverter
+EOT
--- /dev/null
+read_verilog <<EOT
+module top1;
+ localparam a = 8 /*foo*/ 'h ab;
+ localparam b = 8 'h /*foo*/ cd;
+ generate
+ if (a != 8'b10101011) $error("a incorrect!");
+ if (b != 8'b11001101) $error("b incorrect!");
+ endgenerate
+endmodule
+EOT
+logger -expect error "syntax error, unexpected TOK_BASE" 1
+read_verilog <<EOT
+module top2;
+ localparam a = 12'h4 /*foo*/'b0;
+endmodule
+EOT