2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add Octeon+.
* mips-opc.c (IOCT): Include Octeon+.
(IOCTP): New macro.
(mips_builtin_opcodes): Add "saa" and "saad".
bfd/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* archures.c (bfd_mach_mips_octeonp): New macro.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c (I_mipsocteonp): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeonp.
* elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
(mips_mach_extensions): Add bfd_mach_mips_octeonp.
include/opcodes/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
(INSN_OCTEONP): New macro.
(CPU_OCTEONP): New macro.
(OPCODE_IS_MEMBER): Add Octeon+.
(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
gas/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* config/tc-mips.c (CPU_IS_OCTEON): New macro function.
(CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
(NO_ISA_COP): Likewise.
(macro) <ld_st>: Add support when off0 is true.
Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
(mips_cpu_info_table): Add octeon+.
* doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
gas/testsuite/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* gas/mips/mips.exp: Add octeon+ for an architecture.
Run octeon-saa-saad test.
(run_dump_test_arch): For Octeon architectures, also try octeon@.
* gas/mips/octeon-pref.d: Remove -march=octeon from command line.
* gas/mips/octeon.d: Likewise.
* gas/mips/octeon-saa-saad.d: New file.
* gas/mips/octeon-saa-saad.s: New file
+2011-11-29 Andrew Pinski <apinski@cavium.com>
+
+ * archures.c (bfd_mach_mips_octeonp): New macro.
+ * bfd-in2.h: Regenerate.
+ * bfd/cpu-mips.c (I_mipsocteonp): New enum value.
+ (arch_info_struct): Add bfd_mach_mips_octeonp.
+ * elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
+ (mips_mach_extensions): Add bfd_mach_mips_octeonp.
+
2011-11-23 Tristan Gingold <gingold@adacore.com>
* vms-lib.c (get_idxlen): Add comments. Fix type in sizeof.
.#define bfd_mach_mips_loongson_3a 3003
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mips_octeon 6501
+.#define bfd_mach_mips_octeonp 6601
.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mips_loongson_3a 3003
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon 6501
+#define bfd_mach_mips_octeonp 6601
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
I_loongson_2f,
I_loongson_3a,
I_mipsocteon,
+ I_mipsocteonp,
I_xlr,
I_micromips
};
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
+ N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
};
break;
case bfd_mach_mips_octeon:
+ case bfd_mach_mips_octeonp:
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
break;
static const struct mips_mach_extension mips_mach_extensions[] = {
/* MIPS64r2 extensions. */
+ { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
/* MIPS64 extensions. */
+2011-11-29 Andrew Pinski <apinski@cavium.com>
+
+ * config/tc-mips.c (CPU_IS_OCTEON): New macro function.
+ (CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
+ (NO_ISA_COP): Likewise.
+ (macro) <ld_st>: Add support when off0 is true.
+ Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
+ (mips_cpu_info_table): Add octeon+.
+ * doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
+
2011-11-25 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (do_t_mov_cmp): Allow MOV lowreg, lowreg when no CPU
/* True if CPU has a ror instruction. */
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
+/* True if CPU is in the Octeon family */
+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP)
+
/* True if CPU has seq/sne and seqi/snei instructions. */
-#define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
+#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
/* True if CPU does not implement the all the coprocessor insns. For these
CPUs only those COP insns are accepted that are explicitly marked to be
available on the CPU. ISA membership for COP insns is ignored. */
-#define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
+#define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU))
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
int ust = 0;
int lp = 0;
int ab = 0;
+ int off0 = 0;
int off;
offsetT maxnum;
bfd_reloc_code_real_type r;
tempreg, tempreg, breg);
breg = tempreg;
}
- if (!off12)
+ if (off0)
+ {
+ if (offset_expr.X_add_number == 0)
+ tempreg = breg;
+ else
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN,
+ "t,r,j", tempreg, breg, BFD_RELOC_LO16);
+ macro_build (NULL, s, fmt, treg, tempreg);
+ }
+ else if (!off12)
macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s, fmt,
treg, (unsigned long) offset_expr.X_add_number, breg);
}
- else if (off12)
+ else if (off12 || off0)
{
- /* A 12-bit offset field is too narrow to be used for a low-part
- relocation, so load the whole address into the auxillary
- register. In the case of "A(b)" addresses, we first load
- absolute address "A" into the register and then add base
- register "b". In the case of "o(b)" addresses, we simply
- need to add 16-bit offset "o" to base register "b", and
+ /* A 12-bit or 0-bit offset field is too narrow to be used
+ for a low-part relocation, so load the whole address into
+ the auxillary register. In the case of "A(b)" addresses,
+ we first load absolute address "A" into the register and
+ then add base register "b". In the case of "o(b)" addresses,
+ we simply need to add 16-bit offset "o" to base register "b", and
offset_reloc already contains the relocations associated
with "o". */
if (ab)
tempreg, breg, -1,
offset_reloc[0], offset_reloc[1], offset_reloc[2]);
expr1.X_add_number = 0;
- macro_build (NULL, s, fmt,
- treg, (unsigned long) expr1.X_add_number, tempreg);
+ if (off0)
+ macro_build (NULL, s, fmt, treg, tempreg);
+ else
+ macro_build (NULL, s, fmt,
+ treg, (unsigned long) expr1.X_add_number, tempreg);
}
else if (mips_pic == NO_PIC)
{
}
break;
+
+ case M_SAA_AB:
+ ab = 1;
+ case M_SAA_OB:
+ s = "saa";
+ off0 = 1;
+ fmt = "t,(b)";
+ goto ld_st;
+ case M_SAAD_AB:
+ ab = 1;
+ case M_SAAD_OB:
+ s = "saad";
+ off0 = 1;
+ fmt = "t,(b)";
+ goto ld_st;
+
/* New code added to support COPZ instructions.
This code builds table entries out of the macros in mip_opcodes.
R4000 uses interlocks to handle coproc delays.
/* Cavium Networks Octeon CPU core */
{ "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
+ { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
/* RMI Xlr */
{ "xlr", 0, ISA_MIPS64, CPU_XLR },
loongson2f,
loongson3a,
octeon,
+octeon+,
xlr
@end quotation
+2011-11-29 Andrew Pinski <apinski@cavium.com>
+
+ * gas/mips/mips.exp: Add octeon+ for an architecture.
+ Run octeon-saa-saad test.
+ (run_dump_test_arch): For Octeon architectures, also try octeon@.
+ * gas/mips/octeon-pref.d: Remove -march=octeon from command line.
+ * gas/mips/octeon.d: Likewise.
+ * gas/mips/octeon-saa-saad.d: New file.
+ * gas/mips/octeon-saa-saad.s: New file
+
2011-11-25 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/mov-highregs-any.d: New testcase.
set format [expr { $elf ? "elf" : $ecoff ? "ecoff" : "aout" }]
set proparch [lindex [mips_arch_properties $arch 0] 0]
- foreach prefix [list ${proparch}@${format}@ ${proparch}@ ${format}@] {
+ set prefixes [list ${proparch}@${format}@ ${proparch}@ ]
+ if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
+ lappend prefixes octeon@
+ lappend prefixes octeon@${format}@
+ }
+ lappend prefixes ${format}@
+ foreach prefix ${prefixes} {
set archname ${prefix}${name}
if { [file exists "$srcdir/$subdir/${archname}.d"] } {
set name $archname
mips_arch_create octeon 64 mips64r2 {} \
{ -march=octeon -mtune=octeon } { -mmips:octeon } \
{ mips64octeon*-*-* }
+mips_arch_create octeonp 64 octeon {} \
+ { -march=octeon+ -mtune=octeon+ } { -mmips:octeon+ } \
+ { }
mips_arch_create xlr 64 mips64 {} \
{ -march=xlr -mtune=xlr } { -mmips:xlr }
run_dump_test "loongson-3a-3"
run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
+ run_dump_test_arches "octeon-saa-saad" [mips_arch_list_matching octeonp]
run_list_test_arches "octeon-ill" "" \
[mips_arch_list_matching octeon]
run_dump_test_arches "octeon-pref" [mips_arch_list_matching octeon]
-#as: -march=octeon -64 -mfix-cn63xxp1
+#as: -64 -mfix-cn63xxp1
#objdump: -M reg-names=numeric -dr
#name: MIPS octeon-pref mfix-cn63xxp1
--- /dev/null
+#objdump: -d -r --show-raw-insn
+#name: MIPS-OCTEON octeon_saa_saad
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*: 70450018 saa a1,\(v0\)
+.*: 70860019 saad a2,\(a0\)
+.*: 00000000 nop
+.*: 70450018 saa a1,\(v0\)
+.*: 70860019 saad a2,\(a0\)
+.*: 00000000 nop
+.*: 3c010000 lui at,0x0
+ 18: R_MIPS_HI16 .text
+.*: 24210000 addiu at,at,0
+ 1c: R_MIPS_LO16 .text
+.*: 70250018 saa a1,\(at\)
+.*: 3c010000 lui at,0x0
+ 24: R_MIPS_HI16 .text
+.*: 24210000 addiu at,at,0
+ 28: R_MIPS_LO16 .text
+.*: 70220019 saad v0,\(at\)
+.*: 00000000 nop
+.*: 3c011234 lui at,0x1234
+.*: 24215678 addiu at,at,22136
+.*: 70240018 saa a0,\(at\)
+.*: 3c011234 lui at,0x1234
+.*: 24215678 addiu at,at,22136
+.*: 70240019 saad a0,\(at\)
+.*: 00000000 nop
+.*: 24811234 addiu at,a0,4660
+.*: 70250018 saa a1,\(at\)
+.*: 2401003c li at,60
+.*: 70260019 saad a2,\(at\)
+.*: 00000000 nop
+.*: 3c010012 lui at,0x12
+.*: 00240821 addu at,at,a0
+.*: 24213456 addiu at,at,13398
+.*: 70250018 saa a1,\(at\)
+.*: 24c11234 addiu at,a2,4660
+.*: 70260018 saa a2,\(at\)
+.*: 00000000 nop
+.*: 24a15678 addiu at,a1,22136
+.*: 70240019 saad a0,\(at\)
+.*: 3c010056 lui at,0x56
+.*: 00250821 addu at,at,a1
+.*: 24217891 addiu at,at,30865
+.*: 70250019 saad a1,\(at\)
+.*: 00000000 nop
+.*: 24a10000 addiu at,a1,0
+ 9c: R_MIPS_LO16 .text
+.*: 70240018 saa a0,\(at\)
+.*: 24a10000 addiu at,a1,0
+ a4: R_MIPS_LO16 .text
+.*: 70240019 saad a0,\(at\)
+.*: 00000000 nop
--- /dev/null
+ .text
+foo:
+ saa $5,($2)
+ saad $6,($4)
+ nop
+
+ saa $5,0($2)
+ saad $6,0($4)
+ nop
+
+ saa $5, foo
+ saad $2, foo
+ nop
+
+ saa $4, 0x12345678
+ saad $4, 0x12345678
+ nop
+
+ saa $5, 0x1234($4)
+ saad $6, 60($0)
+ nop
+
+ saa $5, 0x123456($4)
+ saa $6, 0x1234($6)
+ nop
+
+ saad $4, 0x5678($5)
+ saad $5, 0x567891($5)
+ nop
+
+ saa $4, %lo(foo)($5)
+ saad $4, %lo(foo)($5)
+ nop
-#as: -march=octeon -64
+#as: -64
#objdump: -M reg-names=numeric -dr
#name: MIPS octeon instructions
+2011-11-29 Andrew Pinski <apinski@cavium.com>
+
+ * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
+ (INSN_OCTEONP): New macro.
+ (CPU_OCTEONP): New macro.
+ (OPCODE_IS_MEMBER): Add Octeon+.
+ (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
+
2011-11-01 DJ Delorie <dj@redhat.com>
* rl78.h: New file.
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0c20
+#define INSN_CHIP_MASK 0xc3ff0e20
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
+#define INSN_OCTEONP 0x00000200
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f010
#define CPU_LOONGSON_2F 3002
#define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501
+#define CPU_OCTEONP 6601
#define CPU_XLR 887682 /* decimal 'XLR' */
/* Test for membership in an ISA including chip specific ISAs. INSN
&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|| (cpu == CPU_OCTEON \
&& ((insn)->membership & INSN_OCTEON) != 0) \
+ || (cpu == CPU_OCTEONP \
+ && ((insn)->membership & INSN_OCTEONP) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
|| 0) /* Please keep this term for easier source merging. */
M_S_DOB,
M_S_DAB,
M_S_S,
+ M_SAA_AB,
+ M_SAA_OB,
+ M_SAAD_AB,
+ M_SAAD_OB,
M_SC_AB,
M_SC_OB,
M_SCD_AB,
+2011-11-29 Andrew Pinski <apinski@cavium.com>
+
+ * mips-dis.c (mips_arch_choices): Add Octeon+.
+ * mips-opc.c (IOCT): Include Octeon+.
+ (IOCTP): New macro.
+ (mips_builtin_opcodes): Add "saa" and "saad".
+
2011-11-25 Pierre Muller <muller@ics.u-strasbg.fr>
* mips-dis.c (print_insn_micromips): Rename local variable iprintf
ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
mips_hwr_names_numeric },
+ { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
+ ISA_MIPS64R2 | INSN_OCTEON | INSN_OCTEONP, mips_cp0_names_numeric,
+ NULL, 0, mips_hwr_names_numeric },
+
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64 | INSN_XLR,
mips_cp0_names_xlr,
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
-#define IOCT INSN_OCTEON
+#define IOCT (INSN_OCTEON | INSN_OCTEONP)
+#define IOCTP INSN_OCTEONP
#define XLR INSN_XLR
#define G1 (T3 \
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
+{"saa", "t,o(b)", 0, (int) M_SAA_OB, INSN_MACRO, 0, IOCTP },
+{"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP },
+{"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
+{"saad", "t,o(b)", 0, (int) M_SAAD_OB, INSN_MACRO, 0, IOCTP },
+{"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP },
+{"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
projects / binutils-gdb.git / commitdiff