i965: Fixup Sandybridge GS packet from doc updates.

diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 47702f7f3029ca2db6924d2439a89bd0900e054a..761059c96a0670b1f542da07ed457a2527c6cdeb 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -39,8 +39,8 @@ upload_gs_state(struct brw_context *brw)
    struct intel_context *intel = &brw->intel;
 
    if (brw->gs.prog_bo) {
-      BEGIN_BATCH(6);
-      OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
+      BEGIN_BATCH(7);
+      OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
       OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
       OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
                (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
@@ -50,10 +50,11 @@ upload_gs_state(struct brw_context *brw)
                (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
                GEN6_GS_STATISTICS_ENABLE);
+      OUT_BATCH(GEN6_GS_ENABLE);
       ADVANCE_BATCH();
    } else {
-      BEGIN_BATCH(6);
-      OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2));
+      BEGIN_BATCH(7);
+      OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
       OUT_BATCH(0); /* prog_bo */
       OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
                (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
@@ -63,6 +64,7 @@ upload_gs_state(struct brw_context *brw)
                (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
       OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
                GEN6_GS_STATISTICS_ENABLE);
+      OUT_BATCH(0);
       ADVANCE_BATCH();
    }