MIPS/opcodes: Add legacy CP1 control register names

The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly.  Do not update the TX39 though as it did not have an FPU.

	opcodes/
	* mips-dis.c (mips_cp1_names_mips): New variable.
	(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
	for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
	"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
	"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
	"r12000", "r14000", "r16000", "mips5", "loongson2e", and
	"loongson2f".

	gas/
	* testsuite/gas/mips/cp1-names-r3900.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.
	* testsuite/gas/mips/branch-misc-3.d: Update disassembly
	according to changes to opcodes.
	* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
	* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
	* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
	* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
	* testsuite/gas/mips/trunc.d: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 77dd8f740a6ebc69f37470c0d39e799007a72853..89a1acd27688422f1528a9478bcafd9c6548c754 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
+
+       * testsuite/gas/mips/cp1-names-r3900.d: New test.
+       * testsuite/gas/mips/mips.exp: Run the new test.
+       * testsuite/gas/mips/branch-misc-3.d: Update disassembly
+       according to changes to opcodes.
+       * testsuite/gas/mips/cp1-names-r3000.d: Likewise.
+       * testsuite/gas/mips/cp1-names-r4000.d: Likewise.
+       * testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
+       * testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
+       * testsuite/gas/mips/trunc.d: Likewise.
+
 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 
        * testsuite/gas/mips/cp0c.d: New test.

diff --git a/gas/testsuite/gas/mips/branch-misc-3.d b/gas/testsuite/gas/mips/branch-misc-3.d
index 754ed20e7b5375300422a3712a25920350c94b70..aad4d4c494e81779a5927d6c238794e45afecaca 100644 (file)
--- a/gas/testsuite/gas/mips/branch-misc-3.d
+++ b/gas/testsuite/gas/mips/branch-misc-3.d
@@ -7,11 +7,11 @@
 Disassembly .*:
 
 0+00 <.*>:
-.*     ctc1    a0,\$31
+.*     ctc1    a0,c1_fcsr
 .*     b       .*
 .*     nop
 #
-.*     ctc1    a0,\$31
+.*     ctc1    a0,c1_fcsr
 .*     nop
 .*     nop
 .*     bc1t    .*
@@ -26,13 +26,13 @@ Disassembly .*:
 .*     bc1t    .*
 .*     nop
 #
-.*     ctc1    a0,\$31
+.*     ctc1    a0,c1_fcsr
 .*     addiu   a1,a1,1
 .*     nop
 .*     bc1t    .*
 .*     nop
 #
-.*     ctc1    a0,\$31
+.*     ctc1    a0,c1_fcsr
 .*     addiu   a1,a1,1
 .*     addiu   a2,a2,1
 .*     bc1t    .*
@@ -43,7 +43,7 @@ Disassembly .*:
 .*     bc1t    .*
 .*     nop
 #
-.*     ctc1    a0,\$31
+.*     ctc1    a0,c1_fcsr
 .*     addiu   a1,a1,1
 .*     addiu   a2,a2,1
 .*     bc1t    .*

diff --git a/gas/testsuite/gas/mips/cp1-names-r3000.d b/gas/testsuite/gas/mips/cp1-names-r3000.d
index 25b5bfbc6b51900a7212ca122730ca0b06190206..247f959b77b5cac168ea93885991b6d4aca6da6b 100644 (file)
--- a/gas/testsuite/gas/mips/cp1-names-r3000.d
+++ b/gas/testsuite/gas/mips/cp1-names-r3000.d
@@ -8,7 +8,7 @@
 .*: +file format .*mips.*
 
 Disassembly of section \.text:
-0+0000 <[^>]*> 44c00000        ctc1    \$0,\$0
+0+0000 <[^>]*> 44c00000        ctc1    \$0,c1_fir
 0+0004 <[^>]*> 44c00800        ctc1    \$0,\$1
 0+0008 <[^>]*> 44c01000        ctc1    \$0,\$2
 0+000c <[^>]*> 44c01800        ctc1    \$0,\$3
@@ -39,8 +39,8 @@ Disassembly of section \.text:
 0+0070 <[^>]*> 44c0e000        ctc1    \$0,\$28
 0+0074 <[^>]*> 44c0e800        ctc1    \$0,\$29
 0+0078 <[^>]*> 44c0f000        ctc1    \$0,\$30
-0+007c <[^>]*> 44c0f800        ctc1    \$0,\$31
-0+0080 <[^>]*> 44400000        cfc1    \$0,\$0
+0+007c <[^>]*> 44c0f800        ctc1    \$0,c1_fcsr
+0+0080 <[^>]*> 44400000        cfc1    \$0,c1_fir
 0+0084 <[^>]*> 44400800        cfc1    \$0,\$1
 0+0088 <[^>]*> 44401000        cfc1    \$0,\$2
 0+008c <[^>]*> 44401800        cfc1    \$0,\$3
@@ -71,5 +71,5 @@ Disassembly of section \.text:
 0+00f0 <[^>]*> 4440e000        cfc1    \$0,\$28
 0+00f4 <[^>]*> 4440e800        cfc1    \$0,\$29
 0+00f8 <[^>]*> 4440f000        cfc1    \$0,\$30
-0+00fc <[^>]*> 4440f800        cfc1    \$0,\$31
+0+00fc <[^>]*> 4440f800        cfc1    \$0,c1_fcsr
        \.\.\.

diff --git a/gas/testsuite/gas/mips/cp1-names-r3900.d b/gas/testsuite/gas/mips/cp1-names-r3900.d
new file mode 100644 (file)
index 0000000..abb86e6
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-r3900.d
@@ -0,0 +1,5 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=r3900
+#name: MIPS CP1 register disassembly (r3900)
+#as: -32 -march=r3900
+#source: cp1-names.s
+#dump: cp1-names-numeric.d

diff --git a/gas/testsuite/gas/mips/cp1-names-r4000.d b/gas/testsuite/gas/mips/cp1-names-r4000.d
index a1030a2a97e3456a3f09d7b68d7ae32b556764d6..5368425385493a91e3ca5f181d30c0a9d78d717e 100644 (file)
--- a/gas/testsuite/gas/mips/cp1-names-r4000.d
+++ b/gas/testsuite/gas/mips/cp1-names-r4000.d
@@ -8,7 +8,7 @@
 .*: +file format .*mips.*
 
 Disassembly of section \.text:
-0+0000 <[^>]*> 44c00000        ctc1    \$0,\$0
+0+0000 <[^>]*> 44c00000        ctc1    \$0,c1_fir
 0+0004 <[^>]*> 44c00800        ctc1    \$0,\$1
 0+0008 <[^>]*> 44c01000        ctc1    \$0,\$2
 0+000c <[^>]*> 44c01800        ctc1    \$0,\$3
@@ -39,8 +39,8 @@ Disassembly of section \.text:
 0+0070 <[^>]*> 44c0e000        ctc1    \$0,\$28
 0+0074 <[^>]*> 44c0e800        ctc1    \$0,\$29
 0+0078 <[^>]*> 44c0f000        ctc1    \$0,\$30
-0+007c <[^>]*> 44c0f800        ctc1    \$0,\$31
-0+0080 <[^>]*> 44400000        cfc1    \$0,\$0
+0+007c <[^>]*> 44c0f800        ctc1    \$0,c1_fcsr
+0+0080 <[^>]*> 44400000        cfc1    \$0,c1_fir
 0+0084 <[^>]*> 44400800        cfc1    \$0,\$1
 0+0088 <[^>]*> 44401000        cfc1    \$0,\$2
 0+008c <[^>]*> 44401800        cfc1    \$0,\$3
@@ -71,5 +71,5 @@ Disassembly of section \.text:
 0+00f0 <[^>]*> 4440e000        cfc1    \$0,\$28
 0+00f4 <[^>]*> 4440e800        cfc1    \$0,\$29
 0+00f8 <[^>]*> 4440f000        cfc1    \$0,\$30
-0+00fc <[^>]*> 4440f800        cfc1    \$0,\$31
+0+00fc <[^>]*> 4440f800        cfc1    \$0,c1_fcsr
        \.\.\.

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 5bbd7617306a3e958fae608887a11a5c614cf028..aebfe3d05bb68611c304858566f246a3794e7008 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1340,6 +1340,7 @@ if { [istarget mips*-*-vxworks*] } {
 
     run_dump_test "cp1-names-numeric"
     run_dump_test "cp1-names-r3000"
+    run_dump_test "cp1-names-r3900"
     run_dump_test "cp1-names-r4000" \
                  { { {name} {(r4000)} } { {objdump} {-M cp0-names=r4000} } }
     run_dump_test "cp1-names-r4000" \

diff --git a/gas/testsuite/gas/mips/relax-swap1-mips1.d b/gas/testsuite/gas/mips/relax-swap1-mips1.d
index e76c651bd944ba0984dc28c887878bd4533be64d..980ed4e0a60f36a214c9828ecfdeb222b439976a 100644 (file)
--- a/gas/testsuite/gas/mips/relax-swap1-mips1.d
+++ b/gas/testsuite/gas/mips/relax-swap1-mips1.d
@@ -240,10 +240,10 @@ Disassembly of section \.text:
 [      ]*2f0: R_MIPS_LO16      \.text
 0+02f4 <[^>]*> jr      at
 0+02f8 <[^>]*> nop
-0+02fc <[^>]*> cfc1    v0,\$31
+0+02fc <[^>]*> cfc1    v0,c1_fcsr
 0+0300 <[^>]*> b       00000000 <foo>
 0+0304 <[^>]*> nop
-0+0308 <[^>]*> cfc1    v0,\$31
+0+0308 <[^>]*> cfc1    v0,c1_fcsr
 0+030c <[^>]*> lw      at,2\(gp\)
 [      ]*30c: R_MIPS_GOT16     \.text
 0+0310 <[^>]*> nop
@@ -251,10 +251,10 @@ Disassembly of section \.text:
 [      ]*314: R_MIPS_LO16      \.text
 0+0318 <[^>]*> jr      at
 0+031c <[^>]*> nop
-0+0320 <[^>]*> ctc1    v0,\$31
+0+0320 <[^>]*> ctc1    v0,c1_fcsr
 0+0324 <[^>]*> b       00000000 <foo>
 0+0328 <[^>]*> nop
-0+032c <[^>]*> ctc1    v0,\$31
+0+032c <[^>]*> ctc1    v0,c1_fcsr
 0+0330 <[^>]*> lw      at,2\(gp\)
 [      ]*330: R_MIPS_GOT16     \.text
 0+0334 <[^>]*> nop

diff --git a/gas/testsuite/gas/mips/relax-swap1-mips2.d b/gas/testsuite/gas/mips/relax-swap1-mips2.d
index 6318318f0b7781d928021f764c588ef02da782c7..057fbd2a72ad434aa983c2849988585aaeea0b76 100644 (file)
--- a/gas/testsuite/gas/mips/relax-swap1-mips2.d
+++ b/gas/testsuite/gas/mips/relax-swap1-mips2.d
@@ -211,20 +211,20 @@ Disassembly of section \.text:
 [      ]*27c: R_MIPS_LO16      \.text
 0+0280 <[^>]*> jr      at
 0+0284 <[^>]*> lwc1    \$f0,0\(a0\)
-0+0288 <[^>]*> cfc1    v0,\$31
+0+0288 <[^>]*> cfc1    v0,c1_fcsr
 0+028c <[^>]*> b       00000000 <foo>
 0+0290 <[^>]*> nop
-0+0294 <[^>]*> cfc1    v0,\$31
+0+0294 <[^>]*> cfc1    v0,c1_fcsr
 0+0298 <[^>]*> lw      at,2\(gp\)
 [      ]*298: R_MIPS_GOT16     \.text
 0+029c <[^>]*> addiu   at,at,860
 [      ]*29c: R_MIPS_LO16      \.text
 0+02a0 <[^>]*> jr      at
 0+02a4 <[^>]*> nop
-0+02a8 <[^>]*> ctc1    v0,\$31
+0+02a8 <[^>]*> ctc1    v0,c1_fcsr
 0+02ac <[^>]*> b       00000000 <foo>
 0+02b0 <[^>]*> nop
-0+02b4 <[^>]*> ctc1    v0,\$31
+0+02b4 <[^>]*> ctc1    v0,c1_fcsr
 0+02b8 <[^>]*> lw      at,2\(gp\)
 [      ]*2b8: R_MIPS_GOT16     \.text
 0+02bc <[^>]*> addiu   at,at,860

diff --git a/gas/testsuite/gas/mips/trunc.d b/gas/testsuite/gas/mips/trunc.d
index d71458538f93a890ec76e44d1d75a4344c0d626a..472e18b3c512ad48db8d3b7cafcb31a3c2483609 100644 (file)
--- a/gas/testsuite/gas/mips/trunc.d
+++ b/gas/testsuite/gas/mips/trunc.d
@@ -7,25 +7,25 @@
 .*: +file format .*mips.*
 
 Disassembly of section .text:
-0+0000 <[^>]*> cfc1    a0,\$31
-0+0004 <[^>]*> cfc1    a0,\$31
+0+0000 <[^>]*> cfc1    a0,c1_fcsr
+0+0004 <[^>]*> cfc1    a0,c1_fcsr
 0+0008 <[^>]*> nop
 0+000c <[^>]*> ori     at,a0,0x3
 0+0010 <[^>]*> xori    at,at,0x2
-0+0014 <[^>]*> ctc1    at,\$31
+0+0014 <[^>]*> ctc1    at,c1_fcsr
 0+0018 <[^>]*> nop
 0+001c <[^>]*> cvt.w.d \$f4,\$f6
-0+0020 <[^>]*> ctc1    a0,\$31
+0+0020 <[^>]*> ctc1    a0,c1_fcsr
 0+0024 <[^>]*> nop
-0+0028 <[^>]*> cfc1    a0,\$31
-0+002c <[^>]*> cfc1    a0,\$31
+0+0028 <[^>]*> cfc1    a0,c1_fcsr
+0+002c <[^>]*> cfc1    a0,c1_fcsr
 0+0030 <[^>]*> nop
 0+0034 <[^>]*> ori     at,a0,0x3
 0+0038 <[^>]*> xori    at,at,0x2
-0+003c <[^>]*> ctc1    at,\$31
+0+003c <[^>]*> ctc1    at,c1_fcsr
 0+0040 <[^>]*> nop
 0+0044 <[^>]*> cvt.w.s \$f4,\$f6
-0+0048 <[^>]*> ctc1    a0,\$31
+0+0048 <[^>]*> ctc1    a0,c1_fcsr
 0+004c <[^>]*> nop
 0+0050 <[^>]*> nop
 #pass

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2151bb6a8bc5fd0134729fdc2bd5bc589c90a189..795391d61b51877cd8066b8773e5db25cf2068dc 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
+
+       * mips-dis.c (mips_cp1_names_mips): New variable.
+       (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
+       for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
+       "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
+       "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
+       "r12000", "r14000", "r16000", "mips5", "loongson2e", and
+       "loongson2f".
+
 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 
        * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 75231ae0a83a0d1501e0b6269382ab1b81e58c70..591caf11e28929aefb5b34dbec29e4a2192e4f3d 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -182,6 +182,18 @@ static const char * const mips_cp0_names_mips3264[32] =
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
+static const char * const mips_cp1_names_mips[32] =
+{
+  "c1_fir",       "$1",           "$2",           "$3",
+  "$4",           "$5",           "$6",           "$7",
+  "$8",           "$9",           "$10",          "$11",
+  "$12",          "$13",          "$14",          "$15",
+  "$16",          "$17",          "$18",          "$19",
+  "$20",          "$21",          "$22",          "$23",
+  "$24",          "$25",          "$26",          "$27",
+  "$28",          "$29",          "$30",          "c1_fcsr"
+};
+
 static const char * const mips_cp1_names_mips3264[32] =
 {
   "c1_fir",       "c1_ufr",       "$2",           "$3",
@@ -466,76 +478,76 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_hwr_names_numeric },
 
   { "r3000",   1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
-    mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_r3000, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r3900",   1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
     mips_cp0_names_r3900, NULL, 0, mips_cp1_names_numeric,
     mips_hwr_names_numeric },
   { "r4000",   1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
-    mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_r4000, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r4010",   1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "vr4100",  1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "vr4111",  1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "vr4120",  1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r4300",   1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r4400",   1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
-    mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_r4000, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r4600",   1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r4650",   1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r5000",   1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "vr5400",  1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "vr5500",  1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r5900",   1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
-    mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_r5900, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r6000",   1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "rm7000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "rm9000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r8000",   1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r10000",  1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r12000",  1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r14000",  1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "r16000",  1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
   { "mips5",   1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
     mips_hwr_names_numeric },
 
   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
@@ -636,11 +648,11 @@ const struct mips_arch_choice mips_arch_choices[] =
 
   { "loongson2e",   1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
     ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
-    NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
+    NULL, 0, mips_cp1_names_mips, mips_hwr_names_numeric },
 
   { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
     ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
-    NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
+    NULL, 0, mips_cp1_names_mips, mips_hwr_names_numeric },
 
   /* The loongson3a is an alias of gs464 for compatibility */
   { "loongson3a",   1, bfd_mach_mips_gs464, CPU_GS464,