r600g: add polygon offset support

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 7d304f5ae80a2e0161036e04dc5226458c85fcdf..43b3e40fad11735abee26b5ac6813a47ff0aacf7 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1142,7 +1142,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_DP3,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
        {TGSI_OPCODE_DP4,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
        {TGSI_OPCODE_DST,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_MIN,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_MIN,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
        {TGSI_OPCODE_MAX,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
        {TGSI_OPCODE_SLT,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
        {TGSI_OPCODE_SGE,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index f0abafd6c21eb23a9dd1965c9ae074ba898e52c6..72c0ac5dd1a9f19131c06718c0526b9c3d498ab7 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -765,8 +765,37 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 {
        const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
+       const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
        struct r600_screen *rscreen = rctx->screen;
        struct radeon_state *rstate;
+       float offset_units = 0, offset_scale = 0;
+       char depth = 0;
+       unsigned offset_db_fmt_cntl = 0;
+
+       if (fb->zsbuf) {
+               offset_units = state->offset_units;
+               offset_scale = state->offset_scale * 12.0f;
+               switch (fb->zsbuf->texture->format) {
+               case PIPE_FORMAT_Z24X8_UNORM:
+               case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+                       depth = -24;
+                       offset_units *= 2.0f;
+                       break;
+               case PIPE_FORMAT_Z32_FLOAT:
+                       depth = -23;
+                       offset_units *= 1.0f;
+                       offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+                       break;
+               case PIPE_FORMAT_Z16_UNORM:
+                       depth = -16;
+                       offset_units *= 4.0f;
+                       break;
+               default:
+                       R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
+                       return NULL;
+               }
+       }
+       offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 
        rctx->flat_shade = state->flatshade;
        rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
@@ -777,7 +806,10 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
        rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
                        S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
                        S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
-                       S_028814_FACE(!state->front_ccw);
+                       S_028814_FACE(!state->front_ccw) |
+                       S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+                       S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+                       S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
        rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
        rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
        rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
@@ -790,12 +822,12 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
        rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
        rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
        rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
-       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
+       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
        rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
-       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
-       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
-       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
-       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
+       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
+       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
+       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
+       rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
        if (radeon_state_pm4(rstate)) {
                radeon_state_decref(rstate);
                return NULL;

diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 6085596ea8ddb8b1fb935863a22b40b076c7aa32..24cb8593f74a549973de3023de17b866138551f6 100644 (file)
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -539,6 +539,29 @@
 #define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
 #define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
 #define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
+#define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
+#define   C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
+#define   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
+#define   G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
+#define   C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define   S_028E00_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E00_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E00_SCALE                               0x00000000
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define   S_028E04_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E04_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E04_OFFSET                              0x00000000
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define   S_028E08_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E08_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E08_SCALE                               0x00000000
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E0C_OFFSET                              0x00000000
 #define R_028A40_VGT_GS_MODE                         0x028A40
 #define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
 #define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)