Fix annulled unconditional branches

--HG--
extra : convert_revision : 698b0ce38c7a47306f97df2cc80cdae4a51b22c7

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 3c5236661be79a7244879263e4d3992fb0ef4958..0c8d77362b7a38c478965bd7300a3d1987d080d5 100644 (file)
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -41,20 +41,45 @@ decode OP default Unknown::unknown()
         0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
         format BranchN
         {
-            0x1: decode BPCC
+            0x1: decode COND2
             {
-                0x0: bpcci(19, {{
-                    if(passesCondition(Ccr<3:0>, COND2))
-                        NNPC = xc->readPC() + disp;
-                    else
-                        handle_annul
-                }});
-                0x2: bpccx(19, {{
-                    if(passesCondition(Ccr<7:4>, COND2))
+                //Branch Always
+                0x8: decode A
+                {
+                    0x0: b(19, {{
                         NNPC = xc->readPC() + disp;
-                    else
-                        handle_annul
-                }});
+                    }});
+                    0x1: b(19, {{
+                        NPC = xc->readPC() + disp;
+                        NNPC = NPC + 4;
+                    }}, ',a');
+                }
+                //Branch Never
+                0x0: decode A
+                {
+                    0x0: bn(19, {{
+                        NNPC = NNPC;//Don't do anything
+                    }});
+                    0x1: bn(19, {{
+                        NPC = xc->readNextPC() + 4;
+                        NNPC = NPC + 4;
+                    }}, ',a');
+                }
+                default: decode BPCC
+                {
+                    0x0: bpcci(19, {{
+                        if(passesCondition(Ccr<3:0>, COND2))
+                            NNPC = xc->readPC() + disp;
+                        else
+                            handle_annul
+                    }});
+                    0x2: bpccx(19, {{
+                        if(passesCondition(Ccr<7:4>, COND2))
+                            NNPC = xc->readPC() + disp;
+                        else
+                            handle_annul
+                    }});
+                }
             }
             0x2: bicc(22, {{
                 if(passesCondition(Ccr<3:0>, COND2))

diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index 8a3f05173fca5acd90ce5db0550d4113d7e977e6..2c206354b40f7def2ea8848dc279efa1302e84eb 100644 (file)
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -224,7 +224,6 @@ let {{
 
 // Primary format for branch instructions:
 def format Branch(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
         (usesImm, code, immCode,
          rString, iString) = splitOutImm(code)
         iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
@@ -246,7 +245,14 @@ def format Branch(code, *opt_flags) {{
 def format BranchN(bits, code, *opt_flags) {{
         code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, opt_flags)
+        new_opt_flags = []
+        for flag in opt_flags:
+            if flag == ',a':
+                name += ',a'
+                Name += 'Annul'
+            else:
+                new_opt_flags += flag
+        iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, new_opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         exec_output = BranchExecute.subst(iop)