update SVSTATE to 64 bit length

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 0723a2d77b7dcdd77a0739a2665285d2b3754542..9c4cde8666a5c07a5115bbfd0ba943a31ef774f0 100644 (file)
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -68,7 +68,7 @@ Pseudo-code:
 
     # for convenience, VL to be calculated and stored in SVSTATE
     vlen <- [0] * 7
-    SVSTATE[0:31] <- [0] * 32
+    SVSTATE[0:63] <- [0] * 64
     # clear out all SVSHAPEs
     SVSHAPE0[0:31] <- [0] * 32
     SVSHAPE1[0:31] <- [0] * 32

diff --git a/openpower/isatables/sprs.csv b/openpower/isatables/sprs.csv
index 5acc87f6162098ee7e5fcb24aae48daf08669787..54d0a0cd5c34c5552e266880ea08a5b22d92ce16 100644 (file)
--- a/openpower/isatables/sprs.csv
+++ b/openpower/isatables/sprs.csv
@@ -63,7 +63,7 @@ Idx,SPR,priv_mtspr,priv_mfspr,len
 349,AMOR,hypv,hypv,64
 446,TIR,-,yes,64
 464,PTCR,hypv,hypv,64
-704,SVSTATE,no,no,32
+704,SVSTATE,no,no,64
 720,PRTBL,yes,yes,64
 721,SVSRR0,yes,yes,32
 722,SVSHAPE0,yes,yes,32

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index 1d4808383be8595580a5342793a52dba92828557..efdf441cebd4dfc59cd9b4e1b68e457b5571e519 100644 (file)
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -47,7 +47,7 @@ class IssuerDecode2ToOperand(RecordObject):
         # current "state" (TODO: this in its own Record)
         self.msr = Signal(64, reset_less=True)
         self.cia = Signal(64, reset_less=True)
-        self.svstate = Signal(32, reset_less=True)
+        self.svstate = Signal(64, reset_less=True)
 
         # instruction, type and decoded information
         self.insn = Signal(32, reset_less=True) # original instruction

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index dcab72f6f7d2e4fb64b07ec291c057ddf3b82c63..79f2e70ff49d5886cca6e448133e25ad3b123dfa 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -253,7 +253,7 @@ class PC:
 # Simple-V: see https://libre-soc.org/openpower/sv
 class SVP64State:
     def __init__(self, init=0):
-        self.spr = SelectableInt(init, 32)
+        self.spr = SelectableInt(init, 64)
         # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
         self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
         self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
@@ -1598,6 +1598,7 @@ class ISACaller:
         vl = self.svstate.vl.asint(msb0=True)
         log ("    srcstep", srcstep)
         log ("    dststep", dststep)
+        log ("         vl", vl)
 
         # check if end reached (we let srcstep overrun, above)
         # nothing needs doing (TODO zeroing): just do next instruction

diff --git a/src/openpower/sv/svstate.py b/src/openpower/sv/svstate.py
index 6052a8f17f7ece3e5ce05ccafdee526ae069d450..9d593e182f34a7d7a243d576cdac1b8696a4fff6 100644 (file)
--- a/src/openpower/sv/svstate.py
+++ b/src/openpower/sv/svstate.py
@@ -23,6 +23,7 @@ from nmigen import Signal
 class SVSTATERec(RecordObject):
     def __init__(self, name=None):
         super().__init__(name=name)
+        self.rsvd = Signal(32) # TODO
         self.svstep = Signal(2)
         self.subvl = Signal(2)
         self.dststep = Signal(7)