Extend LiteDRAM VHDL wrapper to allow more than one clock line

This is necessary for the upcoming Arctic Tern system enablement

diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl
index 7df3dfd6aab444690b2164495c613cc8b0e7a241..f65125a43670394a8e5ac7fca52d48153760e23e 100644 (file)
--- a/core_dram_tb.vhdl
+++ b/core_dram_tb.vhdl
@@ -121,6 +121,7 @@ begin
             DRAM_ABITS => 24,
             DRAM_ALINES => 1,
             DRAM_DLINES => 16,
+            DRAM_CKLINES => 1,
             DRAM_PORT_WIDTH => 128,
             PAYLOAD_FILE => DRAM_INIT_FILE,
             PAYLOAD_SIZE => ROM_SIZE

diff --git a/dram_tb.vhdl b/dram_tb.vhdl
index 571bd70bda32661b1c1b00db52da155d6464d41b..ca7c90b82a9ff54fabc2338cbe24fb16d302b56c 100644 (file)
--- a/dram_tb.vhdl
+++ b/dram_tb.vhdl
@@ -44,6 +44,7 @@ begin
             DRAM_ABITS => 24,
             DRAM_ALINES => 1,
             DRAM_DLINES => 16,
+            DRAM_CKLINES => 1,
             DRAM_PORT_WIDTH => 128,
             PAYLOAD_FILE => DRAM_INIT_FILE,
             PAYLOAD_SIZE => DRAM_INIT_SIZE

diff --git a/fpga/top-acorn-cle-215.vhdl b/fpga/top-acorn-cle-215.vhdl
index bcbadad77991bbb099df6adeaead4da5ef5eb958..9183125b4a28e6eb83c1ea1d7074f486adf8e1c4 100644 (file)
--- a/fpga/top-acorn-cle-215.vhdl
+++ b/fpga/top-acorn-cle-215.vhdl
@@ -272,6 +272,7 @@ begin
                DRAM_ABITS => 26,
                DRAM_ALINES => 16,
                 DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
                 DRAM_PORT_WIDTH => 128,
                 PAYLOAD_FILE => RAM_INIT_FILE,
                 PAYLOAD_SIZE => PAYLOAD_SIZE

diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index 68d1e898250bb71fa2bd87deb42add89e8466c16..41255069e184cada536c875ef74d7feec8c0de6d 100644 (file)
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -85,8 +85,8 @@ entity toplevel is
         ddram_dq      : inout std_ulogic_vector(15 downto 0);
         ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
         ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
-        ddram_clk_p   : out std_ulogic;
-        ddram_clk_n   : out std_ulogic;
+        ddram_clk_p   : out std_ulogic_vector(0 downto 0);
+        ddram_clk_n   : out std_ulogic_vector(0 downto 0);
         ddram_cke     : out std_ulogic;
         ddram_odt     : out std_ulogic;
         ddram_reset_n : out std_ulogic
@@ -346,6 +346,7 @@ begin
                 DRAM_ABITS => 24,
                 DRAM_ALINES => 14,
                 DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
                 DRAM_PORT_WIDTH => 128,
                 PAYLOAD_FILE => RAM_INIT_FILE,
                 PAYLOAD_SIZE => PAYLOAD_SIZE

diff --git a/fpga/top-genesys2.vhdl b/fpga/top-genesys2.vhdl
index fcd190f71a1c135d7a9e978b8bd87e9a23c72438..fc1218e286d75ab6708ea0ffd51783840b8fa8e5 100644 (file)
--- a/fpga/top-genesys2.vhdl
+++ b/fpga/top-genesys2.vhdl
@@ -275,6 +275,7 @@ begin
                DRAM_ABITS => 25,
                DRAM_ALINES => 15,
                 DRAM_DLINES => 32,
+                DRAM_CKLINES => 1,
                 DRAM_PORT_WIDTH => 256,
                 PAYLOAD_FILE => RAM_INIT_FILE,
                 PAYLOAD_SIZE => PAYLOAD_SIZE

diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index 86bdd1199133af22d4224e242654ee0ce52cdaad..485b3a7e1fcab4d58b1d5f6e3902c63921e95942 100644 (file)
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -263,6 +263,7 @@ begin
                DRAM_ABITS => 25,
                DRAM_ALINES => 15,
                 DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
                 DRAM_PORT_WIDTH => 128,
                 PAYLOAD_FILE => RAM_INIT_FILE,
                 PAYLOAD_SIZE => PAYLOAD_SIZE

diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl
index 5823f199149e5350e0202405c8ebf15934b7b4c5..0923f6fb1c218bd3e2203b42e9bd59bb03142321 100644 (file)
--- a/litedram/extras/litedram-wrapper-l2.vhdl
+++ b/litedram/extras/litedram-wrapper-l2.vhdl
@@ -13,6 +13,7 @@ entity litedram_wrapper is
        DRAM_ABITS      : positive;
        DRAM_ALINES     : natural;
        DRAM_DLINES     : natural;
+       DRAM_CKLINES    : natural;
        DRAM_PORT_WIDTH : positive;
 
         -- Pseudo-ROM payload
@@ -69,8 +70,8 @@ entity litedram_wrapper is
         ddram_dq      : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
         ddram_dqs_p   : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
         ddram_dqs_n   : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
-        ddram_clk_p   : out std_ulogic;
-        ddram_clk_n   : out std_ulogic;
+        ddram_clk_p   : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
+        ddram_clk_n   : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
         ddram_cke     : out std_ulogic;
         ddram_odt     : out std_ulogic;
         ddram_reset_n : out std_ulogic
@@ -93,8 +94,8 @@ architecture behaviour of litedram_wrapper is
         ddram_dq                       : inout std_ulogic_vector(DRAM_DLINES-1 downto 0);
         ddram_dqs_p                    : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
         ddram_dqs_n                    : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0);
-        ddram_clk_p                    : out std_ulogic;
-        ddram_clk_n                    : out std_ulogic;
+        ddram_clk_p                    : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
+        ddram_clk_n                    : out std_ulogic_vector(DRAM_CKLINES-1 downto 0);
         ddram_cke                      : out std_ulogic;
         ddram_odt                      : out std_ulogic;
         ddram_reset_n                  : out std_ulogic;

diff --git a/litedram/extras/sim_litedram.vhdl b/litedram/extras/sim_litedram.vhdl
index 00162409bc5b8e57e2ce47d7b13e8f523e351276..295c111cd9a2a3c7ed7b7279781ddc275b880882 100644 (file)
--- a/litedram/extras/sim_litedram.vhdl
+++ b/litedram/extras/sim_litedram.vhdl
@@ -102,8 +102,8 @@ entity litedram_core is
        ddram_dq                       : inout std_ulogic_vector(15 downto 0);
        ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
        ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p                    : out std_ulogic;
-       ddram_clk_n                    : out std_ulogic;
+       ddram_clk_p                    : out std_ulogic_vector(0 downto 0);
+       ddram_clk_n                    : out std_ulogic_vector(0 downto 0);
        ddram_cke                      : out std_ulogic;
        ddram_odt                      : out std_ulogic;
        ddram_reset_n                  : out std_ulogic;