command: address/length in bytes

diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py
index 88dd700e644fef1ffdca19c129aaefb2cee4ad2f..a669a2a18cd438700df7ad925c204749998e04a9 100644 (file)
--- a/lib/sata/command/__init__.py
+++ b/lib/sata/command/__init__.py
@@ -16,19 +16,22 @@ rx_to_tx = [
 ]
 
 class SATACommandTX(Module):
-       def __init__(self, transport):
+       def __init__(self, transport, sector_size):
                self.sink = sink = Sink(command_tx_description(32))
                self.to_rx = to_rx = Source(tx_to_rx)
                self.from_rx = from_rx = Sink(rx_to_tx)
 
                ###
 
+               sector_bits = log2_int(sector_size)
+               dwords_bits = 2
+
                self.comb += [
                        transport.sink.pm_port.eq(0),
                        transport.sink.features.eq(0),
-                       transport.sink.lba.eq(sink.address),  # XXX need adaptation?
+                       transport.sink.lba.eq(sink.address[sector_bits-dwords_bits:]),
                        transport.sink.device.eq(0xe0),
-                       transport.sink.count.eq(sink.length), # XXX need adaptation?
+                       transport.sink.count.eq(sink.length[sector_bits-dwords_bits:]),
                        transport.sink.icc.eq(0),
                        transport.sink.control.eq(0),
                ]
@@ -113,7 +116,7 @@ class SATACommandTX(Module):
                ]
 
 class SATACommandRX(Module):
-       def __init__(self, transport):
+       def __init__(self, transport, sector_size):
                self.source = source = Source(command_rx_description(32))
                self.to_tx = to_tx = Source(rx_to_tx)
                self.from_tx = from_tx = Sink(tx_to_rx)
@@ -214,9 +217,9 @@ class SATACommandRX(Module):
                ]
 
 class SATACommand(Module):
-       def __init__(self, transport):
-               self.submodules.tx = SATACommandTX(transport)
-               self.submodules.rx = SATACommandRX(transport)
+       def __init__(self, transport, sector_size=512):
+               self.submodules.tx = SATACommandTX(transport, sector_size)
+               self.submodules.rx = SATACommandRX(transport, sector_size)
                self.comb += [
                        self.rx.to_tx.connect(self.tx.from_rx),
                        self.tx.to_rx.connect(self.rx.from_tx)

diff --git a/lib/sata/test/command_tb.py b/lib/sata/test/command_tb.py
index 59a786edc2f270c543b51936bc677f98a2861267..bd5092772bb4721e0caca777d83ad0ee069fbebe 100644 (file)
--- a/lib/sata/test/command_tb.py
+++ b/lib/sata/test/command_tb.py
@@ -109,7 +109,7 @@ class TB(Module):
                                link_random_level=25, link_debug=False,
                                transport_debug=False, transport_loopback=False,
                                command_debug=False,
-                               mem_debug=True)
+                               hdd_debug=True)
                self.submodules.link = SATALink(self.hdd.phy)
                self.submodules.transport = SATATransport(self.link)
                self.submodules.command = SATACommand(self.transport)
@@ -129,11 +129,11 @@ class TB(Module):
 
        def gen_simulation(self, selfp):
                self.hdd.allocate_mem(0x00000000, 64*1024*1024)
-               write_data = [i for i in range(128)]
-               write_packet = CommandTXPacket(write=1, address=1024, length=len(write_data), data=write_data)
+               write_data = [i for i in range(512//4)]
+               write_packet = CommandTXPacket(write=1, address=0, length=len(write_data), data=write_data)
                yield from self.streamer.send(write_packet)
                yield from self.logger.receive()
-               read_packet = CommandTXPacket(read=1, address=1024, length=len(write_data))
+               read_packet = CommandTXPacket(read=1, address=0, length=len(write_data))
                yield from self.streamer.send(read_packet)
                yield from self.logger.receive()
                read_data = self.logger.packet