(no commit message)

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index dc9324bb5652ea688a4d4f5b367e59a0f1f94cd7..c9762566064ec8dc8f5743346369096edc322d56 100644 (file)
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -300,7 +300,15 @@ which has a workaround below (merge to single bit mask)
 
 **LD/ST Indexed**
 
-TODO
+Element-Striding is specifically enabled on RA and RB being
+scalar.  If VL=1 behaviour is also activated then this is potentially
+interfered with, except that, again, RT may be set as a vector destination.
+
+
+```
+    if svctx.ldstmode == elementstride:
+        EA = ireg[RA] + ireg[RB]*j   # register-strided
+```
 
 ## answers to 4, loops/uses