fix predicate mask case when smask was zero but mmode was not

quick/easy way: use predicates.get((mmode,smask)) and if empty skip
added stack of tests, 1P and 2P, to test_pysvp64dis.py

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index ad7486ae4745026256c9a37326b563aafc857175..065eec98499daefcf15f7ea9c1e81ebb533c146b 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1373,6 +1373,8 @@ class MRBaseRM(BaseRM):
 
 class NormalLDSTBaseRM(BaseRM):
     def specifiers(self, record):
+        # these go in inverse order. calculable as: "8<<(3-width)"
+        # TODO later: fp operations would be ew=fp16 ew=bf16 ew=fp32
         widths = {
             0b11: "8",
             0b10: "16",
@@ -1398,14 +1400,17 @@ class NormalLDSTBaseRM(BaseRM):
             (1, 0b111): "ns",
         }
 
+        # predication - single and twin.  use "m=" if same otherwise sm/dm
         mmode = int(self.mmode)
         mask = int(self.mask)
         if record.svp64.ptype is _SVPtype.P2:
             (smask, dmask) = (int(self.smask), mask)
         else:
             (smask, dmask) = (mask, mask)
-        if all((smask, dmask)) and (smask == dmask):
-            yield f"m={predicates[(mmode, smask)]}"
+        if smask == dmask:
+            m = predicates.get((mmode, smask))
+            if m:
+                yield "m="+m
         else:
             sw = predicates.get((mmode, smask))
             dw = predicates.get((mmode, dmask))
@@ -1414,6 +1419,7 @@ class NormalLDSTBaseRM(BaseRM):
             if dw:
                 yield f"dm={dw}"
 
+        # elwidths: use "w=" if same otherwise dw/sw
         dw = int(self.elwidth)
         sw = int(self.ewsrc)
         if all((dw, sw)) and (dw == sw):

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 4cd442b5fd2a2dddfd58f05682b6aa9dbe4691a0..8fbd0203bdb187c404ec7e20bc3c2335556defe6 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -231,6 +231,23 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_15_predicates(self):
+        expected = [
+                    "sv.add./m=r3 *3,*7,*11",
+                    "sv.add./m=1<<r3 *3,*7,*11",
+                    "sv.add./m=~r10 *3,*7,*11",
+                    "sv.add./m=so *3,*7,*11",
+                    "sv.add./m=ne *3,*7,*11",
+                    "sv.add./m=lt *3,*7,*11",
+                    "sv.add. *3,*7,*11",
+                    "sv.extsw/m=r30 3,7",
+                    "sv.extsw/sm=r30/dm=~r30 3,7",
+                    "sv.extsw/sm=gt/dm=eq 3,7",
+                    "sv.extsw/sm=~r3 3,7",
+                    "sv.extsw/dm=r30 3,7",
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()