microwatt_tutorial: Fix formatting

diff --git a/HDL_workflow/microwatt_tutorial.mdwn b/HDL_workflow/microwatt_tutorial.mdwn
index e43f3d7e7a593f6af13502c99ac8204b15460a8c..03cb94bcde245aaa296cba19e6544698c60294b2 100644 (file)
--- a/HDL_workflow/microwatt_tutorial.mdwn
+++ b/HDL_workflow/microwatt_tutorial.mdwn
@@ -27,8 +27,9 @@ Make sure verilator binaries in $PATH:
 
 (GHDLSYNTH needs to be redefined because the Makefile has default `ghdl.so`,
 but somewhere else '.so' gets appended. You may see the following error if you
-don't redefine: `ERROR: Can't load module `./ghdl.so':
-/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`)
+don't redefine:
+`ERROR: Can't load module
+./ghdl.so':/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`)
 
 To run the Verilator simulation, set verilator as the target: