i965/vs: Fix message setup for array read/writes on pre-gen6.

We were passing an MRF as the source argument, instead of using the
implied move and putting the MRF number in the proper place in the
instruction encoding.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 61a1092bbff187db28586fd422ac9f9580acffde..ac1ef0d878107e94119f1f150ad41dd10523444d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -391,14 +391,9 @@ vec4_visitor::generate_scratch_read(vec4_instruction *inst,
                                    struct brw_reg dst,
                                    struct brw_reg index)
 {
-   if (intel->gen >= 6) {
-      brw_push_insn_state(p);
-      brw_set_mask_control(p, BRW_MASK_DISABLE);
-      brw_MOV(p,
-             retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
-             retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
-      brw_pop_insn_state(p);
-   }
+   struct brw_reg header = brw_vec8_grf(0, 0);
+
+   gen6_resolve_implied_move(p, &header, inst->base_mrf);
 
    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
                                     index);
@@ -417,7 +412,9 @@ vec4_visitor::generate_scratch_read(vec4_instruction *inst,
     */
    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
    brw_set_dest(p, send, dst);
-   brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
+   brw_set_src0(p, send, header);
+   if (intel->gen < 6)
+      send->header.destreg__conditionalmod = inst->base_mrf;
    brw_set_dp_read_message(p, send,
                           255, /* binding table index: stateless access */
                           BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@@ -433,19 +430,14 @@ vec4_visitor::generate_scratch_write(vec4_instruction *inst,
                                     struct brw_reg src,
                                     struct brw_reg index)
 {
+   struct brw_reg header = brw_vec8_grf(0, 0);
+
    /* If the instruction is predicated, we'll predicate the send, not
     * the header setup.
     */
    brw_set_predicate_control(p, false);
 
-   if (intel->gen >= 6) {
-      brw_push_insn_state(p);
-      brw_set_mask_control(p, BRW_MASK_DISABLE);
-      brw_MOV(p,
-             retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
-             retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
-      brw_pop_insn_state(p);
-   }
+   gen6_resolve_implied_move(p, &header, inst->base_mrf);
 
    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
                                     index);
@@ -468,7 +460,9 @@ vec4_visitor::generate_scratch_write(vec4_instruction *inst,
     */
    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
    brw_set_dest(p, send, dst);
-   brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
+   brw_set_src0(p, send, header);
+   if (intel->gen < 6)
+      send->header.destreg__conditionalmod = inst->base_mrf;
    brw_set_dp_write_message(p, send,
                            255, /* binding table index: stateless access */
                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
@@ -508,6 +502,8 @@ vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
    brw_set_dest(p, send, dst);
    brw_set_src0(p, send, header);
+   if (intel->gen < 6)
+      send->header.destreg__conditionalmod = inst->base_mrf;
    brw_set_dp_read_message(p, send,
                           SURF_INDEX_VERT_CONST_BUFFER,
                           BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,