# starting point, and specific parameters can be overridden in the
# specific instantiations.
-class L1Cache(BaseCache):
+class L1Cache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
class L1_DCache(L1Cache):
pass
-class L2Cache(BaseCache):
+class L2Cache(Cache):
assoc = 8
hit_latency = 20
response_latency = 20
tgts_per_mshr = 12
write_buffers = 8
-class IOCache(BaseCache):
+class IOCache(Cache):
assoc = 8
hit_latency = 50
response_latency = 50
tgts_per_mshr = 12
forward_snoops = False
-class PageTableWalkerCache(BaseCache):
+class PageTableWalkerCache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
branchPred = O3_ARM_v7a_BP()
# Instruction Cache
-class O3_ARM_v7a_ICache(BaseCache):
+class O3_ARM_v7a_ICache(Cache):
hit_latency = 1
response_latency = 1
mshrs = 2
is_read_only = True
# Data Cache
-class O3_ARM_v7a_DCache(BaseCache):
+class O3_ARM_v7a_DCache(Cache):
hit_latency = 2
response_latency = 2
mshrs = 6
# TLB Cache
# Use a cache as a L2 TLB
-class O3_ARM_v7aWalkCache(BaseCache):
+class O3_ARM_v7aWalkCache(Cache):
hit_latency = 4
response_latency = 4
mshrs = 6
is_read_only = True
# L2 Cache
-class O3_ARM_v7aL2(BaseCache):
+class O3_ARM_v7aL2(Cache):
hit_latency = 12
response_latency = 12
mshrs = 16
numtesters += t * m
# Define a prototype L1 cache that we scale for all successive levels
-proto_l1 = BaseCache(size = '32kB', assoc = 4,
- hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8)
+proto_l1 = Cache(size = '32kB', assoc = 4,
+ hit_latency = 1, response_latency = 1,
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
sys.exit(1)
# Define a prototype L1 cache that we scale for all successive levels
-proto_l1 = BaseCache(size = '32kB', assoc = 4,
- hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8)
+proto_l1 = Cache(size = '32kB', assoc = 4,
+ hit_latency = 1, response_latency = 1,
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
# Base L1 Cache Definition
# ====================
-class L1(BaseCache):
+class L1(Cache):
latency = options.l1latency
mshrs = 12
tgts_per_mshr = 8
# Base L2 Cache Definition
# ----------------------
-class L2(BaseCache):
+class L2(Cache):
latency = options.l2latency
mshrs = 92
tgts_per_mshr = 16
# Base L1 Cache Definition
# ====================
-class L1(BaseCache):
+class L1(Cache):
latency = options.l1latency
mshrs = 12
tgts_per_mshr = 8
# Base L2 Cache Definition
# ----------------------
-class L2(BaseCache):
+class L2(Cache):
latency = options.l2latency
mshrs = 92
tgts_per_mshr = 16
+++ /dev/null
-# Copyright (c) 2012-2013, 2015 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-from m5.params import *
-from m5.proxy import *
-from MemObject import MemObject
-from Prefetcher import BasePrefetcher
-from Tags import *
-
-class BaseCache(MemObject):
- type = 'BaseCache'
- cxx_header = "mem/cache/base.hh"
-
- size = Param.MemorySize("Capacity")
- assoc = Param.Unsigned("Associativity")
-
- hit_latency = Param.Cycles("Hit latency")
- response_latency = Param.Cycles("Latency for the return path on a miss");
-
- max_miss_count = Param.Counter(0,
- "Number of misses to handle before calling exit")
-
- mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
- demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
- tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
- write_buffers = Param.Unsigned(8, "Number of write buffers")
-
- forward_snoops = Param.Bool(True,
- "Forward snoops from mem side to cpu side")
- is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
-
- prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
- prefetch_on_access = Param.Bool(False,
- "Notify the hardware prefetcher on every access (not just misses)")
-
- tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
- sequential_access = Param.Bool(False,
- "Whether to access tags and data sequentially")
-
- cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
- mem_side = MasterPort("Downstream port closer to memory")
-
- addr_ranges = VectorParam.AddrRange([AllMemory],
- "Address range for the CPU-side port (to allow striping)")
-
- system = Param.System(Parent.any, "System we belong to")
--- /dev/null
+# Copyright (c) 2012-2013, 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+# Andreas Hansson
+
+from m5.params import *
+from m5.proxy import *
+from MemObject import MemObject
+from Prefetcher import BasePrefetcher
+from Tags import *
+
+class BaseCache(MemObject):
+ type = 'BaseCache'
+ abstract = True
+ cxx_header = "mem/cache/base.hh"
+
+ size = Param.MemorySize("Capacity")
+ assoc = Param.Unsigned("Associativity")
+
+ hit_latency = Param.Cycles("Hit latency")
+ response_latency = Param.Cycles("Latency for the return path on a miss");
+
+ max_miss_count = Param.Counter(0,
+ "Number of misses to handle before calling exit")
+
+ mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
+ demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
+ tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
+ write_buffers = Param.Unsigned(8, "Number of write buffers")
+
+ forward_snoops = Param.Bool(True,
+ "Forward snoops from mem side to cpu side")
+ is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
+
+ prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
+ prefetch_on_access = Param.Bool(False,
+ "Notify the hardware prefetcher on every access (not just misses)")
+
+ tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
+ sequential_access = Param.Bool(False,
+ "Whether to access tags and data sequentially")
+
+ cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
+ mem_side = MasterPort("Downstream port closer to memory")
+
+ addr_ranges = VectorParam.AddrRange([AllMemory],
+ "Address range for the CPU-side port (to allow striping)")
+
+ system = Param.System(Parent.any, "System we belong to")
+
+class Cache(BaseCache):
+ type = 'Cache'
+ cxx_header = 'mem/cache/cache.hh'
Import('*')
-SimObject('BaseCache.py')
+SimObject('Cache.py')
Source('base.cc')
Source('cache.cc')
{
}
-BaseCache::BaseCache(const Params *p)
+BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
: MemObject(p),
cpuSidePort(nullptr), memSidePort(nullptr),
mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs),
writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0,
MSHRQueue_WriteBuffer),
- blkSize(p->system->cacheLineSize()),
+ blkSize(blk_size),
lookupLatency(p->hit_latency),
forwardLatency(p->hit_latency),
fillLatency(p->response_latency),
;
}
-
-BaseCache *
-BaseCacheParams::create()
-{
- assert(tags);
-
- return new Cache(this);
-}
virtual void regStats();
public:
- typedef BaseCacheParams Params;
- BaseCache(const Params *p);
+ BaseCache(const BaseCacheParams *p, unsigned blk_size);
~BaseCache() {}
virtual void init();
#include "mem/cache/prefetch/base.hh"
#include "sim/sim_exit.hh"
-Cache::Cache(const Params *p)
- : BaseCache(p),
+Cache::Cache(const CacheParams *p)
+ : BaseCache(p, p->system->cacheLineSize()),
tags(p->tags),
prefetcher(p->prefetcher),
doFastWrites(true),
{
}
+Cache*
+CacheParams::create()
+{
+ assert(tags);
+
+ return new Cache(this);
+}
///////////////
//
// MemSidePort
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/tags/base.hh"
+#include "params/Cache.hh"
#include "sim/eventq.hh"
//Forward decleration
public:
/** Instantiates a basic cache object. */
- Cache(const Params *p);
+ Cache(const CacheParams *p);
/** Non-default destructor is needed to deallocate memory. */
virtual ~Cache();
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