(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 3bbdfabfc53382f34f660203b06232d1662bf69c..8c5fafd79c0d4848e9e14ad3fbe2f9573838ceee 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -593,7 +593,9 @@ but select different *bits* of the same CRs
 
 `offs` is defined as CR48 (6x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below).  Arithmetic Rc=1 operations start from CR16 (TBD); FP Rc=1 from CR32 (TBD).
 
-# Twin Predication
+# Appendix
+
+## Twin Predication
 
 This is a novel concept that allows predication to be applied to a single
 source and a single dest register.  The following types of traditional
@@ -624,8 +626,6 @@ Additional unusual capabilities of Twin Predication include a back-to-back
 version of VCOMPRESS-VEXPAND which is effectively the ability to do an
 ordered multiple VINSERT.
 
-# Appendix
-
 ## CR Operations
 
 CRs are slightly more involved than INT or FP registers due to the