must check *implicit* SelType which comes from the keys "in1/in2/in3/CR in"

being SelType.SRC and keys "out/out2/CR out" being SelType.DST
https://bugs.libre-soc.org/show_bug.cgi?id=1098

diff --git a/src/openpower/insndb/core.py b/src/openpower/insndb/core.py
index 68c8ba0a0c0e85ef9503ff1e9523288326b34764..277a5f3d1320917dbcc73119f412a40d12aeddf5 100644 (file)
--- a/src/openpower/insndb/core.py
+++ b/src/openpower/insndb/core.py
@@ -446,13 +446,19 @@ class SVP64Record:
         regs = {}
         seltypes = {}
         for key in keys:
+            # has the word "in", it is a SelType.SRC "out" -> DST
+            # in1/2/3 and CR in are SRC, and must match only against "s:NN"
+            # out/out1 and CR out are DST, and must match only against "d:NN"
+            keytype = _SelType.SRC if ("in" in key) else _SelType.DST
             sel = sels[key] = getattr(self, key)
             reg = regs[key] = _Reg(sel)
             seltypes[key] = _SelType.NONE
             idxs[key] = _SVExtra.NONE
             for (reg, seltype, idx) in extra(reg.alias):
-                if ((idx != idxs[key]) and (idxs[key] is not _SVExtra.NONE)):
-                    raise ValueError(idxs[key])
+                if keytype != seltype: # only check SRC-to-SRC and DST-to-DST
+                    continue
+                if idx != idxs[key] and idxs[key] is not _SVExtra.NONE:
+                    raise ValueError(idx)
                 idxs[key] = idx
                 regs[key] = reg
                 seltypes[key] = seltype

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 08e5d2328e060c12dd3f431e78dc3e66d0b81713..58d41d146c48ebd5a8542177b58407829323706e 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -35,7 +35,7 @@ class SVSTATETestCase(unittest.TestCase):
                                      "'%s' expected '%s'" % (line, expected[i]))
 
 
-    def test_0_add(self):
+    def tst_0_add(self):
         expected = ['addi 1,5,2',
                     'add 1,5,2',
                     'add. 1,5,2',
@@ -44,13 +44,13 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_1_svshape2(self):
+    def tst_1_svshape2(self):
         expected = [
                     'svshape2 12,1,15,5,0,0'
                         ]
         self._do_tst(expected)
 
-    def test_2_d_custom_op(self):
+    def tst_2_d_custom_op(self):
         expected = [
                     'fishmv 12,2',
                     'fmvis 12,97',
@@ -58,7 +58,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_3_sv_isel(self):
+    def tst_3_sv_isel(self):
         expected = [
                     'sv.isel 12,2,3,33',
                     'sv.isel 12,2,3,*33',
@@ -68,7 +68,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_4_sv_crand(self):
+    def tst_4_sv_crand(self):
         expected = [
                     'sv.crand *16,*2,*33',
                     'sv.crand 12,2,33',
@@ -79,21 +79,21 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_5_setvl(self):
+    def tst_5_setvl(self):
         expected = [
                     "setvl 5,4,5,0,1,1",
                     "setvl. 5,4,5,0,1,1",
                         ]
         self._do_tst(expected)
 
-    def test_6_sv_setvl(self):
+    def tst_6_sv_setvl(self):
         expected = [
                     "sv.setvl 5,4,5,0,1,1",
                     "sv.setvl 63,35,5,0,1,1",
                         ]
         self._do_tst(expected)
 
-    def test_7_batch(self):
+    def tst_7_batch(self):
         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
         expected = [
                     "addi 2,2,0",
@@ -167,7 +167,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_8_madd(self):
+    def tst_8_madd(self):
         expected = [
                     "maddhd 5,4,5,3",
                     "maddhdu 5,4,5,3",
@@ -175,7 +175,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_9_fptrans(self):
+    def tst_9_fptrans(self):
         "enumerates a list of fptrans instruction disassembly entries"
         db = Database(find_wiki_dir())
         entries = sorted(sv_binutils_fptrans.collect(db))
@@ -186,7 +186,7 @@ class SVSTATETestCase(unittest.TestCase):
                 lst.append(line)
         self._do_tst(lst)
 
-    def test_10_vec(self):
+    def tst_10_vec(self):
         expected = [
                     "sv.add./vec2 *3,*7,*11",
                     "sv.add./vec3 *3,*7,*11",
@@ -194,7 +194,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_11_elwidth(self):
+    def tst_11_elwidth(self):
         expected = [
                     "sv.add./dw=8 *3,*7,*11",
                     "sv.add./dw=16 *3,*7,*11",
@@ -211,14 +211,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_12_sat(self):
+    def tst_12_sat(self):
         expected = [
                     "sv.add./satu *3,*7,*11",
                     "sv.add./sats *3,*7,*11",
                         ]
         self._do_tst(expected)
 
-    def test_12_mr_r(self):
+    def tst_12_mr_r(self):
         expected = [
                     "sv.add./mrr/vec2 *3,*7,*11",
                     "sv.add./mr/vec2 *3,*7,*11",
@@ -227,14 +227,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_13_RC1(self):
+    def tst_13_RC1(self):
         expected = [
                     "sv.add/ff=RC1 *3,*7,*11",
                     "sv.add/ff=~RC1 *3,*7,*11",
                         ]
         self._do_tst(expected)
 
-    def test_14_rc1_ff_pr(self):
+    def tst_14_rc1_ff_pr(self):
         expected = [
                     "sv.add./ff=eq *3,*7,*11",
                     "sv.add./ff=ns *3,*7,*11",
@@ -246,7 +246,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_15_predicates(self):
+    def tst_15_predicates(self):
         expected = [
                     "sv.add./m=r3 *3,*7,*11",
                     "sv.add./m=1<<r3 *3,*7,*11",
@@ -263,14 +263,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_15_els(self):
+    def tst_15_els(self):
         expected = [
                     "sv.stw/els *4,16(2)",
                     "sv.lfs/els *1,256(4)",
                         ]
         self._do_tst(expected)
 
-    def test_16_bc(self):
+    def tst_16_bc(self):
         """bigger list in test_pysvp64dis_branch.py, this one's "quick"
         """
         expected = [
@@ -290,21 +290,21 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_17_vli(self):
+    def tst_17_vli(self):
         expected = [
                     "sv.add/ff=RC1/vli 3,7,11",
                     "sv.add/ff=~RC1/vli 3,7,11",
                         ]
         self._do_tst(expected)
 
-    def test_18_sea(self):
+    def tst_18_sea(self):
         expected = [
                     "sv.ldux/sea 5,6,7",
                     "sv.ldux/pi/sea 5,6,7",
                         ]
         self._do_tst(expected)
 
-    def test_19_ldst_idx_els(self):
+    def tst_19_ldst_idx_els(self):
         expected = [
                     "sv.stdx/els *4,16,2",
                     "sv.stdx/els/sea *4,16,2",
@@ -313,7 +313,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_20_cmp(self):
+    def tst_20_cmp(self):
         expected = [
                     "sv.cmp *4,1,*0,1",
                     "sv.cmp/ff=eq *4,1,*0,1",
@@ -326,7 +326,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_21_addex(self):
+    def tst_21_addex(self):
         expected = [
                     "addex 5,3,2,0",
                     "sv.addex 5,3,2,0",
@@ -334,7 +334,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_22_ld(self):
+    def tst_22_ld(self):
         expected = [
                     "ld 4,0(5)",
                     "ld 4,16(5)",       # sigh, needs magic-shift (D||0b00)
@@ -342,7 +342,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_23_lq(self):
+    def tst_23_lq(self):
         expected = [
                     "lq 4,0(5)",
                     "lq 4,16(5)",      # ditto, magic-shift (DQ||0b0000)
@@ -351,14 +351,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_24_bc(self):
+    def tst_24_bc(self):
         expected = [
                     "b 0x28",
                     "bc 16,0,-0xb4",
                         ]
         self._do_tst(expected)
 
-    def test_25_stq(self):
+    def tst_25_stq(self):
         expected = [
                     "stq 4,0(5)",
                     "stq 4,8(5)",
@@ -367,13 +367,13 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_26_sv_stq_vector_name(self):
+    def tst_26_sv_stq_vector_name(self):
         expected = [
                     "sv.stq *4,16(*5)", # RSp not recognised as "vector" name
                         ]
         self._do_tst(expected)
 
-    def test_27_sc(self):
+    def tst_27_sc(self):
         expected = [
                     "sc 0",
                     "sc 1",
@@ -382,14 +382,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_28_rfid(self):
+    def tst_28_rfid(self):
         expected = [
                     "rfid",
                     "rfscv",
                         ]
         self._do_tst(expected)
 
-    def test_29_postinc(self):
+    def tst_29_postinc(self):
         expected = [
                     "sv.ldu/pi 5,8(2)",
                     "sv.lwzu/pi *6,8(2)",
@@ -398,7 +398,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_29_dsld_dsrd(self):
+    def tst_29_dsld_dsrd(self):
         expected = [
                     "dsld 5,4,5,3",
                     "dsrd 5,4,5,3",
@@ -411,7 +411,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_30_divmod2du(self):
+    def tst_30_divmod2du(self):
         expected = [
                     "divmod2du 5,4,5,3",
                     "maddedu 5,4,5,3",
@@ -422,7 +422,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_31_sadd_saddw_sadduw(self):
+    def tst_31_sadd_saddw_sadduw(self):
         expected = [
                     "sadd 31,0,0,0",
                     "sadd 0,31,0,0",
@@ -451,7 +451,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_32_ldst_idx_ffirst(self):
+    def tst_32_ldst_idx_ffirst(self):
         expected = [
                     "sv.stdx/ff=RC1 *4,16,2",
                     "sv.stdx/ff=~RC1 *4,16,2",
@@ -460,7 +460,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_33_ldst_imm_ffirst(self):
+    def tst_33_ldst_imm_ffirst(self):
         expected = [
                     "sv.std/ff=RC1 *4,16(2)",
                     "sv.std/ff=~RC1 *4,16(2)",
@@ -469,13 +469,13 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_34_ldst_update_imm_ffirst(self):
+    def tst_34_ldst_update_imm_ffirst(self):
         expected = [
                     "sv.ldu/ff=~RC1/vli *16,0(*17)",
                         ]
         self._do_tst(expected)
 
-    def test_35_ffmadds(self):
+    def tst_35_ffmadds(self):
         expected = [
                     "sv.ffmadds *0,*0,*0",
                         ]
@@ -484,16 +484,16 @@ class SVSTATETestCase(unittest.TestCase):
     def test_36_extras_rlwimi(self):
         self._do_tst(["sv.rlwimi 3, 1, 5, 20, 6"])
 
-    def test_36_extras_rlwimi_(self):
+    def tst_36_extras_rlwimi_(self):
         self._do_tst(["sv.rlwimi. 3, 1, 5, 20, 6"])
 
-    def test_36_extras_rldimi(self):
+    def tst_36_extras_rldimi(self):
         self._do_tst(["sv.rldimi 3, 4, 56, 4"])
 
-    def test_36_extras_rldimi_(self):
+    def tst_36_extras_rldimi_(self):
         self._do_tst(["sv.rldimi. 3, 4, 56, 4"])
 
-    def test_36_extras_fishmv(self):
+    def tst_36_extras_fishmv(self):
         self._do_tst(["sv.fishmv 3, 0x0FD0"])
 
 if __name__ == "__main__":